 Hello and welcome to this training module for the STM32WB liquid crystal display or LCD controller. This controller can be used in a wide variety of applications such as home appliances, medical, automotive and industrial to display either images made up of a large number of pixels, a combination of alphanumeric symbols or various useful predefined symbols such as digits, bells, low battery symbol, arrows, antenna and progress bar. The LCD controller integrated inside STM32WB products provides a control interface for driving external segmented LCD panels. This interface is fully configurable, allowing easy control of any existing monochrome passive LCD panel up to 320 segments available today on the market. The STM32WB allows the LCD controller to operate in all low power modes, but it is off in standby and shutdown modes. Applications benefit from a built-in low-cost solution not requiring any external controller nor external analog components. The step-up converter supplying the VLCD voltage and resistive network dedicated to generate all intermediate voltages are both part of the controller. The advantages of an embedded controller are that it does not require extra power consumption from external controllers and that it fully supports the STM32WB's ultra-low power modes for higher power efficiency. Its flexible and high-level driving capability make it able to support a wide range of LCD displays, even those with a higher capacitive load. The LCD display is made up of several segments, pixels or complete symbols which can be made visible or invisible. Each segment consists of liquid crystal modules aligned between two electrodes, one COM terminal and one SEG terminal. It is equivalent to a capacitor. When a voltage greater than a threshold voltage is applied across the liquid crystal, the segment becomes visible. The waveform across the segment must alternate to avoid a DC current, otherwise the LCD's lifetime may be shortened. The LCD controller offers a fully programmable interface to control a wide range of LCD displays. The flexible frequency generator makes it easier to scale and fine-tune the frame frequency. The LCD controller supports several duty ratios and bias levels to adapt to a wide range of LCD display characteristics. The structure of the resistive network is configurable by software to adapt the drive current to the LCD display used. The voltage output buffers can improve the driving capability for LCD displays with high capacitive load. The LCD controller offers the option to use an internal or external VLCD supply source to match any application constraints. With the double buffer memory, the LCD RAM register which contains pixel information can be updated at any time by the application software without affecting the integrity of the data displayed. Unused segment and common pins can be used as general purpose IOs or for another peripheral. Last but not least, the LCD controller supports all STM32WB low power modes except standby and shutdown modes for optimized application power efficiency. Here is the block diagram of the LCD controller which also shows the interface with the LCD display. This controller is able to drive 176, 44 by 4, or 320, 40 by 8 LCD pixels. It is made up of the frequency generator used to deliver the correct clock frequency to drive the LCD display, the common seg drivers, the LCD RAM which contains pixel information, active and inactive, and the analog step up converter used to adjust the contrast. No external components are required to make the controller work except an external capacitor connected to VLCD when the step up converter is used. The SEL closed. The LCD controller features a highly flexible frequency generator. The LCD clock source is the same as the RTC clock which is either a low speed external 32.768 kHz oscillator, LSE, a low speed internal 32 kHz RC oscillator, LSI, or a high speed external 32 MHz oscillator, HSE divided by 32. The frequency generator allows you to achieve various LCD frame rates starting from an LCD clock source which can vary from 32 kHz to 1 MHz. The clock source must be stable in order to obtain accurate LCD timing and hence minimize DC voltage offset across LCD segments. The input clock LCD CLK can be divided by any value from 16 to 2 to the 15th power times 31. This frequency generator consists of a pre-scaler 16-bit ripple counter and a 16 to 31 clock divider. LCD CLK is first divided by 2 PS, 3 to 0. If a finer resolution rate is required, the div bits 3 to 0 can be used to divide the clock further by 16 to 31. In this way you can roughly scale the frequency and then fine tune it by linearly scaling the clock with the counter. The output of the frequency generator, FCKDIV, constitutes the time base for the entire LCD controller. It is equivalent to the LCD phase frequency. The frame frequency or F-frame is determined by dividing FCKDIV or FLCD by the number of active common terminals or multiplying it by the duty rate. The typical frame frequency must be selected to be within a range of around 30 to 100 Hz. The selected frequency must be a compromise between an acceptable refresh rate that avoids flickering and the power consumption which increases with the frequency. The following table shows examples of frame rate calculations by specifying PS 3 to 0 and DIV 3 to 0 values for different LCD CLK frequencies. The LCD controller generates a type B frame format which maintains 0 volts DC over the two odd and even frames. All COM signals have identical waveforms but a different phase in order to reduce electromagnetic interference. COM-X has its maximum amplitude only during phase X of a frame, that is to say VLCD during odd frames and VSS during even frames. During the other phases the signal amplitude is ¼ VLCD or ¾ VLCD if a ¼ bias is selected, 1 ¾ VLCD or 2 ¾ VLCD if a 1 ¾ bias is selected and 1 ½ if a 1 ½ bias is selected. Each segment terminal is multiplexed, meaning that each one may control up to 8 picture elements depending on the chosen duty rate. For a duty rate of ¼ as shown in this example, a single segment terminal is associated with four common terminals, thus allowing the control of four picture elements. The greater the multiplexed rate, the more segment or picture elements you can drive with a given number of segment terminals. For example, to activate a pixel N connected to COM 2, SEG N must be inactive VSS during phase 2 of the odd frame and active VLCD during phase 2 of the even frame. Actually a pixel is active if the corresponding SEG N line has a voltage opposite that of the COM line, here COM 2, and inactive when the voltages are equal. As a result, the voltage applied between COM 2 and SEG N, which can be observed on the COM 2 minus SEG N waveform, is plus VLCD during phase 2 of the odd frame and minus VLCD during phase 2 of the even frame. The LCD controller offers high contrast control flexibility. The method used to adjust the contrast depends on the LCD supply source. When the step-up converter is selected as VLCD source, the VLCD value can be chosen among a wide set of values from 2.6 to 3.6 volts, which are selectable via the contrast control bits in the LCD FCR register. However, when using an external LCD supply source, the contrast level is adjusted using a programmable dead time where both active COM and SEG terminals are all tied to VSS at the same time between each odd frame and each even frame. As a result, the LCD RMS voltage of the entire frame, odd and even, is reduced, thus decreasing the contrast. Of course, the longer the dead time periods, the lower the contrast. LCD displays are sensitive to root mean square or RMS voltage levels. To turn a segment on, the RMS voltage applied to this segment, here in the example, the potential difference between the COM 2 and SEG N, must be greater than the LCD display threshold voltage, or VTH. The LCD threshold voltage depends on the quality of the liquid used in the LCD panel and the temperature. As a reminder, the optical contrast is defined by the difference in transparency of an LCD segment that is on, dark and an LCD segment that is off, transparent. In other words, by the difference between the RMS voltage of an LCD segment on, VON RMS and the RMS voltage of an LCD segment off, VOFF RMS. Then, the greater the difference between VON RMS and VOFF RMS, the higher the optical contrast. In the same way, the contrast also depends on the level of VON RMS versus the LCD threshold voltage. The greater the difference between VON RMS and VTH, the higher the optical contrast. However, VON RMS and VOFF RMS are directly linked to the multiplex rate or duty ratio used to drive the LCD display. When the number of COM terminals required to drive the LCD display increases, the discrimination ratio, D, the contrast level that the LCD display can achieve, decreases, since the separation between VON RMS and VOFF RMS decreases, and the contrast decreases. As a consequence, to provide a better contrast and a greater separation between VON RMS and VOFF RMS, when the multiplex rate increases, the LCD voltage must be increased. Make sure the LCD controller configuration matches the LCD display needs in terms of segment and common terminals, otherwise this could result in a lower contrast. In the LCD controller, the power supply source may come from either the internal step-up converter or from an external voltage source applied on the VLCD pin. When the step-up converter is selected as VLCD source, the VLCD values can be chosen independently of the VDD value via the contrast control bits in the LCD FCR register. If an external source is selected, the internal boost circuit or step-up converter is automatically disabled to reduce power consumption. In both cases, the intermediate voltage levels required for the common and segment waveforms are generated thanks to resistor networks. One with low-value resistors or RLN for high-drive capability and the other with high-value resistors or RHN for low-drive capability, which are used respectively to increase current during transitions and to reduce power consumption in static state. The RLN divider is enabled when the high-drive resistor bridge is closed. The high-drive resistor bridge can be switched on permanently when the HD bit is set or for only a short period of time thanks to the pulse-on duration or PON feature. The PON bits can figure the time during which RLN is enabled through the HD switch each time the level of common and segment lines change. This flexible LCD drive capability is completed by low-power voltage output buffers in order to again reinforce the ability of the LCD controller to drive very high capacitive loads. These buffers prevent the LCD capacitive load from unacceptably loading the resistor bridge by increasing the charging and discharging of output capacitors or pixels during each transition. In this way the voltage nodes are very stable, no voltage drop, thus drastically improving the signal shapes and the RMS voltage values. These buffers are power consumption optimized. Their consumption is negligible during static phases whereas they are very reactive to provide necessary current required by the LCD load during transitions. To further reduce power consumption when buffers are enabled intermediate voltages are generated by RHN. RLN is automatically disabled regardless of the HD bit or PON bits configuration. Output buffers can be used regardless of the selected LCD supply source internal or external. The LCD pixels are individually controlled by setting or clearing the corresponding bits of the LCD data register. The STM32WB which can control LCD displays with up to 8 common terminals and up to 44 segment terminals to drive 176, 44 by 4 or 320, 40 by 8 LCD pixels uses LCD RAM data registers made up of 16 by 32 bits, 2 32-bit words per COM. To make LCD software efficient and to optimize LCD alphanumeric coding we use a matrix. Each matrix element corresponds to one bit of the LCD RAM register at a ratio of 15 to 0. For example to enable pixel A connected to SEG2 and COM0, M20 must be set to 1. As a result, bit 2 of COM0 in the LCD RAM register is set to 1. Thanks to the double buffer memory feature, the LCD RAM register can be updated at any time by the application without affecting the integrity of the data displayed and without having to use interrupts to control display modifications. The application software can access the first buffer level, LCD RAM. Once its content is modified, it requests the updated information to be moved into the second buffer level, LCD display. This operation is done synchronously with the beginning of the next frame. Two interrupt events are available with the LCD controller. They both share the same interrupt vector. A start of frame interrupt is set each time a new frame starts to help synchronize software events. The update display done interrupt is set once the new LCD RAM data is moved into the second buffer level, LCD display to update the display. This operation is performed synchronously at the beginning of the next frame. The LCD controller supports all STM32L4 low power modes, making it very efficient in terms of power consumption. In standby and shutdown modes, the controller is off. Refer to the training modules for these peripherals linked to the LCD interface. Reset and clock controller or RCC for more information about the LCD controller's clock sources. Interrupts for more information about the mapping of the LCD controller's interrupts. General Purpose IOs or GPIO for more information about the LCD controller's segment and common lines as well as the VLCD PIN. And power controller or PWR for a description of the LCD controller's low power modes.