 This time we're going to be looking at the branch multiplexer and we're going to be interested in the PC plus 4 bit 1 So that will be the next to most least significant bit coming in from the PC plus 4 line This is the bit that would add 2 to an address or not Depending on whether it's fixed at 0 or at 1 First we'll consider what happens when this bit is stuck at 0 This is our program counter plus 4 So it's potentially the next address for another instruction Since all of our addresses have to be multiples of 4 Then they're never going to have that bit turned on anyway So if this bit is stuck at 0, we'll actually never notice And we're happy about that This bit should effectively be stuck at 0 anyway So if the hardware is broken and it can't set that bit to 1 Then it's actually not a problem for us So we're not really going to have any good way to test that Nor will it actually give us a problem So we won't have to worry about that one If this bit is stuck at 1 though Then instead of pulling out the correct address It's going to pull out the address plus 2 every time So this can have some problems for us If we just put all of our instructions into instruction memory The way we normally would Then every time we tried to increment our program counter We'd end up with the next address plus 2 So instead of pulling out the correct instruction We'd pull out the second half of the instruction that we want And the first half of the next instruction They wouldn't be in order and the results would just be horrible They wouldn't do what we wanted them to And chances are they'd crash the machine anyway If the machine is built well Then the instruction memory would notice that You've asked for a word aligned address And it would just reject that Your program would crash So this machine might never run But we could consider what would happen if The instruction memory doesn't check for word aligned addresses Is there perhaps something we could do To make this work? So the obvious thing to try would just be to offset All of the instructions in memory by 2 bytes So this could potentially allow us to run our instructions normally Until we got to a jump or a branch instruction Both of those instructions expect that the Two least significant bits in our address Are also going to be zeros So they're going to try to branch to a regular address Not one that's been offset by 2 So this one doesn't have a really good way to get around it It's possible we could actually structure our code in such a way That you have an instruction that would be valid Both when your instruction is offset by 2 bytes As well as when it's not offset And then you could just fill in some of these As they're needed to help align things Make it so that your code did actually end up Where it needed to be While this is possible This is not the easiest way to fix a processor And this one would probably just be tossed out Recompiling for this would be rather complex And not terribly helpful Our programs would frequently end up with Lots of extra space in them And the compiler may end up having to go to a lot of effort To restructure certain parts of the code So that you can jump places, you can branch places And you can still just walk to that next instruction as well