 A certain professor, Department of Electronics, Walsh Institute, Thalapur. Now, in this video, we are just going to focus on the JFET's characteristics and the JFET parameters. Friend, at this end of video, you should be able to describe the JFET characteristics. Here we mainly focus on the transfer characteristics of the JFET and we are also able to define the JFET parameters. Friend, this is the circuit I use here to plot the transfer characteristics of a JFET here. If you see closely in this circuit, the source is made common between both gate and the drain here. Friend, in this case, in this case of the graph, the voltage from this train to source is not varied by this battery here, which is called as a voltage VDD and we can vary the voltage from gate to source by the battery which is connected from gate to ground here. We are having some meters are in place here. So, this ammeter just measures the current in the drain, the voltage is also measured from drain to source by this voltmeter and we also measure the voltage from gate to source by this voltmeter. In this lecture, we are just going to focus more on the drain characteristics as well as the transfer characteristics here. Friend, the drain characteristics is the graph between the drain current and the voltage from drain to source here. In this graph, we are going to keep the voltage from gate to source as a constant here. Now, we just speak more about, more deep in the transfer characteristics of a JFAT here, which is a graph between the output current which is flowing in the drain and the input voltage which is supplied from gate to source that is voltage VGS. And in this kind of graph, we are keeping this voltage from drain to source constant here. So, friend, this is a small diagram which tells you, we are trying to plot a graph between the current which is flowing in the drain and the voltage which is applied from gate to source. Friend, in this graph plotting here, we are going to make gate to source junction reverse biased here. Friend, the graph nature is like this here. I will just tell you how this graph is plotted here. First of all, if you see this closely, this axis X shows you the current ID and the axis Y shows you the voltage from gate to source. Now, we draw this graph in the second quadrant of, why? Because the voltage from gate to source is now negative, which is making gate to source junction reverse biased here, so that the graph is now coming in the second quadrant that you see. Moreover, the maximum current we are going to witness is a current called as IDSS. And the current can be at low adds, the 0 here and which is at the voltage called as a VP, which is called as a pinch of voltage here. Friend, I use here some terms which is called as IDSS and second is the pinch of voltage VP there. Friend, I hope that you know this, what is IDSS here and what is meaning of VP because I discussed this already in the drain statistics in the last video. Now, these values are shown here on this X-ray plot, IDSS is a condition at which the current in a fade remains constant here and the voltage VP is nothing but that voltage in the JFET at which the width of junction is minimum and so that I am getting the maximum opposition to flow of current here. So, that is the procedure that we discussed already here, that you are going to adjust the voltage from drain to source and here, first adjust the voltage from drain to source to some voltage here, then keep it constant here, then apply voltage between gate to source which is making this gate to source reverse biased, then vary this voltage and get the current which is flowing in the drain in that corresponding emitter which is in the drain terminal. Friend, these are some of the parameters we are going to see from the graph here. Here, I define this current ID, so current ID is now flowing in the drain of the given fade here and which is now expressed as by this formula, friend if you see this closely the shape of this graph is now nothing but a parabola there and we can define this equation for this parabola which is in the form of the current IDSS and the voltage VP for varying conditions for the voltage VDS there, the ID is now given as ID equal to this IDSS is this current into 1 minus VGS upon VP bracket square, friend if you see closely here the output current VG that is ID is also proportional to the voltage which is on the input side from gate to source. You see that the output current is now changing as a square of a voltage on the input side and friend that is why this JFD is normally called as a square law device because the output is a function as a square of an input voltage here, that is normally called as a square law device here, friend if as friend actually the voltage from this gate to source is a reverse bias here. So when you use this voltage in this formula, we take this voltage VGS as a minus VGS here and so that this entire bracket simply comes as 1 plus some term here. Now friend we just going to focus some of things with the JFD parameters here. So these parameters are showing you the electrical behavior of the JFD here. So that 2 or 3 parameters which are more important for us of which the first is the drain resistance here, friend we know here the JFD can be used in different for different applications here. So based upon the circuit conditions we have to use these different parameters here. So first is drain resistance here, it has got 2 different conditions that is suppose my circuit carries both DC voltage and AC voltage here. So in that case we are going to get some resistance offered by the fate has got both values here. One is AC resistance and also a DC resistance here. So friend I will just go for that one. Resistance offered by this fate here for DC voltage conditions here. It is simply a ratio of the voltage which is coming between drain and the source upon the current flowing in the given drain. It is simply called as resistance RDS. And if I suppose take a resistance for AC conditions, this RDS is not taken as the delta VDS and delta ID ratio here. So friend it is quite visible that in the AC conditions we are thinking about the input varying conditions because circuit is applied with some AC voltage here. Secondly we get one more parameter which is called the trans conductance. This is a ratio of the change in the output current to the change in input voltage here. So friend all we know here the output current is called current ID, input is nothing but the voltage VGS there. So it is coming as delta ID upon delta VGS. And final friend we get one more parameter which is called the amplification factor which is called the mu. So mu is a ratio of the output voltage to the input voltage here. So friend all we know here is that VDS is called the output voltage, VGS is called the input voltage. So mu is a parameter that shows me the ratio of the change in output voltage because of the change in the input voltage VGS there. Friend here we rearrange all the terms in this one. Nothing but the ratio of this VDS upon delta ID into delta ID upon delta VGS. So this simply comes as GM into RD. So friend we see that the amplification factor of this JFET is simply depending upon I say simply depending upon the trans conductance of a given FET and registers offered by the given FET for the AC condition. It is not depending upon any circuit components which is a feature of this FET operation friend here. So friend these are my references. I hope this video is helping you to understand some basic concepts here. Thank you for watching this video. Thanks very much.