 Hello, and welcome to this presentation of the STM32 Flash Memory Interface. It covers all the new features of the STM32 Flash Memory. STM32H7 devices embed high-speed embedded memories with a dual-bank flash memory up to two megabytes that can be used for storing programs and data. The flash memory is organized as 266-bit flash words that can be used for storing both code and data constants. Each word consists of one flash word, eight words, 32 bytes, or 256 bits, 10 ECC bits. The STM32H7 series has a flash memory with dual-bank organization supporting simultaneous operations. Two read program erase operations can be executed in parallel on the two banks. The flash memory supports enhanced security features which can be configured using the option bytes. The readout protection, or RDP, the sector write protection, and two PC rock protection areas, one per bank, execute only memory. The flash interface allows swapping bank one and bank two memory mapping. This feature can be used after a firmware upgrade to restart the device on the new firmware after a system reset. The flash interface also allows setting a secure area in each flash bank. The data and programs stored in this area cannot be accessed unless the secure mode is set. The secure area helps isolating secure user code from non-secure application code. Please refer to the specific training about system protections for more details about these protection options. This figure shows the flash memory high-level block diagram. The flash interface implements a dual AXI bus interface for code data accesses and an AHB interface to configure the flash memory interface. The AXI interface can request a read program operation at the same time. The flash memory is organized as 266-bit flash words that can be used for storing both code and data constants. Each word consists of one flash word, eight words, 32 bytes, or 256 bits, and 10 ECC bits. The flash memory is divided into two independent banks. Each bank is organized as follows. A one megabyte user flash memory block containing eight user sections of 128 kilobytes, 4,000 flash words. 128 kilobytes of system flash memory from which the device can boot. This area contains root secure services, or RSS, and the bootloader, which are used respectively for secure or non-secure flash memory programming through one of the following interfaces. USART, USB, or DFU, I2C, SPI, or Ethernet. The system flash memory is reserved for use by ST Microelectronics. It is programmed by ST Microelectronics when the device is manufactured and then protected against spurious program erase operations. For further details, please refer to application note AN2606, STM32 microcontroller system flash memory boot mode, available from www.st.com. Two kilobytes or 64 flash words of user option bytes for user configuration. This area is available only in Bank 1. Unlike user flash memory and system flash memory, it is not mapped to any memory address and can be accessed only through the flash register interface. The table describes the flash memory organization that is divided into two banks, each having a main memory block containing eight sectors of 128 kilobytes each. Each main memory block has a system flash block that contains the system memory, which is reserved for use by ST Microelectronics and contains the boot loader. When selected, the device boots in system memory to execute the boot loader. Two kilobytes or 64 flash words of user option bytes for user configuration available only in Bank 1. The flash interface can be accessed by double word 64 bits, by single word 32 bits, by half word 16 bits, or by byte 8 bits. The flash interface clock must be enabled and running when reading information from flash memory. To ensure correct flash interface read operation, the number of wait states or latency must be correctly configured in the flash ACR register according to the flash memory interface frequency. The flash interface implements a dual AXI bus interface for code data accesses and an AHB interface for flash interface configuration. The AXI interfaces can request a read program operation at the same time. This table shows the correspondence between the number of wait states, the bus clock frequency, and V-core range. After power on, the clock used is the HSI 64 MHz and seven wait states are configured by default in the flash ACR register. The read mechanism is the following. The read command buffer depth is fixed to three requests. When it is full, three read requests queued in the buffer, any new read request will stall the bus interface and consequently the master. Any system read request for data that is not available in the read buffer triggers a flash read operation. This data is buffered inside the read data buffer. If several consecutive read accesses request data that belongs to the same flash data word, 256 bits, data is directly read from the current data read buffer and does not trigger additional flash read operations. The read command queue buffer is free as soon as the last data of the current read transaction is transferred from the flash memory to the read data buffer inside the flash memory interface. Data in flash memory are 266-bit words. 10 ECC bits are added per flash word of 256 bits. The ECC mechanism is based on the SEC-DED algorithm. It supports single error correction and double error detection. When an error is detected and corrected, the SNEC-CERR1 or 2 flag is set in the flash SR1 or 2 register. An interrupt is generated if the SNEC-CERRIE bit is set in the flash CR1 or 2 register. When an ECC error is detected, the address of the failing flash word is saved in the flash ECC FA1 or 2R register. In case of successive error detections, only the address corresponding to the first error will be stored. This register is automatically cleared when the associated flag that generated the error has been reset. When two errors are detected, the DBEC-CERR1 or 2 flag is set in the flash SR1 or 2 register and a bus error is generated. In this case, the received data is not corrected. An interrupt is generated if the DBEC-CERRIE 1 or 2 bit is set in the flash CR1 or 2 register. The flash interface embeds a cyclic redundancy check or CRC hardware module. This module allows checking the integrity of a flash area content. This area can be defined either by sectors or by start or end addresses. Only one CRC check operation on Bank 1 or 2 can be launched at a time. The CRC operation cannot be concurrent with any option byte change operation. This means that if a CRC operation is requested while an option byte change is ongoing, the option byte change operation must be completed before serving the CRC operation and vice versa. The flash interface issues 4, 16, 64 or 256 consecutive flash word read accesses. These transactions are queued into the read command buffer together with other AXI read requests, thus avoiding denial of AXI read commands. The queue command buffer can only contain one CRC command. The recommended sequence to configure a CRC operation in Bank 1 or 2 is the following. 1. Enable the CRC feature by setting the CRC EN bit in the flash CR1 or 2 register. 2. Program the desired data size in the CRC burst field of the flash CRC CR1 or 2 register. 3. Define the flash area on which the CRC has to be computed. 2 solutions are possible. Define the area start and end addresses by programming registers flash CRCS ADD1 or 2R and flash CRC ADD1 or 2R respectively. 4. Select the targeted sectors by setting the CRC bisect bit in the flash CRC CR1 or 2 register and by programming consecutively the target sector numbers in the CRC sect field of the flash CRC CR1 or 2 register. Set the ADD sect bit after each CRC sect programming. 4. Start the CRC operation by setting the start CRC bit. 5. Wait until the CRC busy flag is reset. 6. Retrieve the CRC result in the flash CRC data R register. The CRC can be computed for a whole bank by setting the all bank bit in the flash CRC CR1 or 2 register. The flash memory interface supports multiple program operations. Write to user sectors, erase user sectors, erase bank 1, bank 2 or both banks and change user option bytes. The write accesses issued through the AXI interface can be considered as bufferable and not cashable except that it is not possible to read back the write buffer inside the flash interface. The embedded flash memory can be programmed using in-circuit programming or in application programming. A program or erase operation can be executed on bank 1 while another program or erase operation is executed on bank 2. Note that the programming parallelism is a parameter that must be configured prior to performing a program or erase operation. The user application must configure the programming parameters prior to performing a program or erase operation. Two write operation modes are possible. The simple write sequence recommended for which the steps are 1. Set the PG1 or 2 bit in the flash CR1 or 2 bit register of the targeted bank, bank 1 or 2. 2. Check the protection of the largest memory area. 3. Write one flash word corresponding to 32 byte data starting at 32 byte aligned address. 4. Check that the QW1 or 2 flag has been raised and wait until it is reset. This sequence can be used to program a block in flash memory. 1. Set the PG1 or 2 bit in the flash CR1 or 2 bit register of the corresponding bank, bank 1 or 2. 2. Check the protection of the target memory area. 3. Write successively 32 data bytes flash words until the whole block is transferred. Each flash word must start at a 32 byte aligned address. 3 different status flags located in flash SR1 or 2 registers are available for each bank. They indicate the ongoing write operation status. Bsy1 or 2. This flag indicates that any effective write, erase or option byte change operation is ongoing to the flash memory. QW1 or 2. This flag indicates that a program, erase or option byte change operation is pending. This bit remains high until the write operation is complete. It supersedes the Bsy1 or 2 status bit. WBNE1 or 2. This flag indicates that the write buffer is not empty. It is reset as soon as the write command is queued. If one of the busy flags is active, the MCU cannot switch the D1 domain to stop or standby mode. To release the flash interface, the BsyX and QWX busy bits must be cleared. The user option byte change operation can be used to modify the configuration and the protection settings saved as the flash memory option byte area. The flash interface features two sets of option byte registers. The first register set contains the current values of the option bytes. Their names have the underscore CUR extension. All CUR registers are read only. Their values are automatically loaded after power on or after an option byte change operation. The second register set allows modifying the option bytes. Their names contain the PRG extension. All PRG registers can be accessed in read write mode. Four interrupts can be generated by the flash memory. The end of operation interrupt is triggered when one or more flash program or erase operations is completed successfully. The programming error input is triggered when a flash memory program or erase operation fail. The write protection error interrupt is triggered when a write access is attempted to a write protected area of the flash memory. The operation error interrupt is triggered when an error is detected during a write or erase operation.