 So, welcome to this lecture on programmable logic devices in the course digital system design with PLDs and FPGAs. The last lecture we have seen basically the basic idea behind this evolution that is using the memory as a programmable logic that was way back maybe 20-25 years back. And the evolution of it like from the prom to the PLA to the PAL and we have started seeing one device which is representative not much use but then as I said it enables us to understand the basic architecture. So that we can build and when it comes to the complex PLDs it is very easy to understand that is that is why we are going through it. So let us quickly glance at the last lecture slides. So basic idea in a programmable logic device is to use memory as a programmable logic and I said that suppose you want to implement this x, x or y two variables then you take a two address line memory with one bit. So two address lines will have four locations and the data line is used as output. You write the truth table of the function you want to implement in this memory and that is you know if the memory is in the right mode you supply the address through the data line you can write the location. And when you use it as a logic which in read mode so you supply the inputs like 00 then the data line will get the zero value when it is 01 gets 1 and so on. So basically you write the truth table in a memory with the appropriate size and use address as input, data as the output and the earlier and as I said SRAM cannot be used because it has to be programmed at the power on and when you need a non-volatile kind of memory the solution was to use a PROM this programmable read-only memory. And where this is an address decoder so you have a1 and a0 we are taking a four location 2 bit and it this AND gate is the one which gives all the min terms or the locations and the programmable this is a fixed OR and we program the location the truth table by retaining this fuse or blowing the fuse. If you want a 0 you blow the fuse then it will be grounded if it is 1 you retain the fuse so when that gate is high you get a high voltage okay that is the basic idea. And as I said when say when you program 1 and 1 these two locations and when you give 01 this will be 1 and this output will be 0 because only 1 min term will be high then if there is no diode there will be a short circuit to avoid the reverse flow this diode is put everywhere okay and the fuse itself is blown by applying a negative voltage here for a short duration that will force it to force larger current through the fuse to blow it it is a one time operation. So it is a negative pulse maybe of say if the supply voltage is 5 volt then you apply 5-5 volt depending on the rating okay that is it. So it is a fixed OR and fixed AND and programmable OR so N input will have 2N vertical lines, 2N AND gates each AND gate will have the N inputs which is connected to the appropriate lines to form the min terms. But we said that this was kind of used for address chip select decoding where many a times only one AND gate is used even in Boolean function you do not need all the two rates when min terms you need only part of them. So the next step was to reduce the number of AND gates and when you reduce it has to be made programmable it cannot be fixed that means each AND gate will have connection to all the vertical lines all the inputs and compliments with some kind of programmability but that enables one to not only implement the min terms but the product term that means you do not have to worry about a1 bar a0 bar in your Boolean equation if it can be minimized for some reason say you have these two terms and can be minimized a1 bar then you need to connect only a1 bar to the AND gate this can be kind of blown or disconnected. So that allows us to use the product term and that was the next step so this was the basic idea you have a programmable AND where you can program not only min terms but the product term and programmable OR and that was called PLA programmable logic array and then it turns out that if you have say three AND gates it is possible to disable one AND gate by retaining all the connections. So effectively there is no much need for this the programmable OR with a lot of programming overhead so that was the next evolution so you had this was the last in the evolution the PAL programmable array logic where you have AND gates with programmable connection to all the inputs and its complement but some fixed number of AND gate connected to an OR gate. So it was possible to use say for a1 to implement a Boolean function of up to three product terms if you have only two then you disable this AND gate we will see that how that is done. So that is the evolution started with PROM which is programmable read only memory with a fixed AND all the two raise to AND min terms programmable OR you are programming the content then the programmable AND and programmable OR PLA which turns out that is an overkill this can be somehow absorbed in this structure so that was the programmable AND and fixed and next this is where we kind of stop we have taken the first kind of devices which came about by AMD and Texas and Simmons and even few companies probably they do not exist now and this was a basic structure so you have you can see that you have 32 vertical lines that means 16 inputs and its complement and you can see there are 9 dedicated 10 dedicated inputs and 2 dedicated output one on top and one at the bottom and 6 IOs which can be used as output or input. So that 10 plus 6 is the 16 and 8 is 8 outputs okay 2 dedicated and 6 IOs so naturally this IOs are countered against the input as well as output L indicates this active low output so it means that if you want to implement Y then you have to implement Y bar as the AND or part that need to be taken care in the tool and you can see that each suppose you take this section you have 7 AND gates each has 32 inputs but this is a wired AND gate we will see that it is not that it is a single AND gate with 32 input wired AND gate. And you have a tri-state gate with enable which AND gate controls it so you can permanently enable by kind of removing all the connection then there is a pull up which will make this one and this will be one this will be permanently kind of enable and you want to permanently do what you can do is that you can retain all the connections. So even if there is one input which is connected say A then A and A bar is connected and it will be 0 all the time it will be cut off okay. So we will have a look at a detailed view of this section to understand the architecture that is what we have stopped as I said to enable it you blow all the connection then it is high you retain all the connection then the AND gate output will be 0. The same technique is used suppose you have a Boolean function with only 3 product terms then you implement that you know you give says the inputs at the input then program the connection to implement the various product terms 1, 2, 3 but you do not need 4, 5, 6 and 7. What you do is that you retain all the connections in these AND gates then these will be 0 and that is kind of disabled only these 3 will go to the because this is 0 so it has no effect and you get a function of 3 product terms okay. And this is what we have seen last time this structure as I said is very, very elegant very useful okay. So you have a tri-state gate with enable a product term controlling that enable and the output there is looks like a feedback to this structure so that adds you know that 6 adds to this 10 plus 6 16 and you have 32 16 inputs and it is complement 32 vertical lines okay. So you should know that every AND gate as can form a product term of any of this 32 okay 16 and it is complement and you see here now this has multiple uses okay. Now obviously this can be used as output where you permanently enable this then by say blowing all the connection then this is enabled this is always an output okay. And suppose you want to use it as an input then what you do is that retain all the connections then even if there is one input at least you have to have one input to be able to use it and then the output will be 0 this is cut off. So all this will be a waste it will be permanently cut off but then this can be used as an input that is a case where maybe you have a circuit with more than 10 inputs say you have 12 inputs but you have lesser number of outputs. So that I mean that is good because we do not have so many outputs but we need some input pins then this can be disabled and it can be used as an input okay and this goes waste of course but then you get one additional input that is an idea but more than that you know so it can be used as output it can be used as input but another option is to use it as an IEO under the control of this product term okay. Suppose for whatever reason this is connected to a shared bus or a CPU bus for whatever logic then you see suppose a CPU has a read bar so we connect read bar to this signal so it is available here and we assume that read bar as such is connected to this AND gate okay. So when the read bar is low this is low so this will be cut off then it is used as an input. When the read bar is high only one input is connected this is high and this is an output. So naturally you know you can interface this to a processor bus need not be a processor bus you know it need not be read bar it can be some product term some you can put a condition if this condition AND some other condition or some other I mean AND of various conditions then you can implement that under that condition that will be output or input depending on the need. So it can be output it can be input it can be IEO but you see that this if you look at instead of you know thinking of it as a separate thing like output or input you can view it as this output is coming back to this whole logic okay. So it shows that this as a node can be used with the you know in the other along with the other product term the use is that suppose you have a Boolean function with say 10 product terms then we are not able to implement that here because there are only 7 product terms. So it tells us that you can cascade you know you can have 7 product terms implemented in this section say the output is inverted but it does not matter it gets you know the second bubble second inverter there is a buffer in this line inverter in this line and that inverter you get that signal and that can be connected to this first AND gate here okay. So you get that 7 product terms in this OR gate you implement suppose 3 additional product term in this section so you get 10 product terms. So when there is a need for more than the product terms accommodated in one section you can use this structure to cascade to get more product terms. So that is an additional use of this particular structure again once again this tells us you know going back tells us that this can be used as a feedback okay. So one simple example is that you think of a cross-couple NAND latch okay I hope we have discussed this in the beginning may be somewhere so you have a NAND gate and two NAND gates the output of one NAND gate drives the input of other NAND gates it gets one set input and this get one reset input this output is feeding back the other input other NAND gates input. So straight away you think there is an input which can be connected to one of the AND gate and AND gate output goes through this inverter come back through this inverter goes to the input of the second AND gate and that AND gate also get another input which can be connected because there are so many inputs. So this goes and get double inversion and connect back to this NAND gate so using two sections you can implement a latch if it is required okay of course there will be lot of AND gates wasted but it can be done. So this allows output, input, IOS and the cascading and feedback everything is kind of made possible by just a simple you know elegant architecture. So it is quite nice and so we will summarise this when an IOS structure you want to use as an output you have to enable the tri-state gate and it is enabled by blowing all the input connections of the control AND gate which is nothing but I call this as a control AND gate which controls the enable of the tri-state and which is nothing but a wired AND with pull-up. So it is not an AND gate with multiple input it is a single wire which is wired AND we will see that how that is formed with a pull-up. So if you remove all the connection then it is pulled up 1 then the output is 1 and when you want to use that as an input you disable the tri-state gate retain all connections of the control AND gate then A and A bar is kind of 0 and you can program when you can use it as an IO under the control of a control product term in the control AND gate okay and you are able to enable any AND gate suppose in the 7 AND gates you can disable 3 of them if you want only use 4 by retaining all the input connections in those AND gates. You can cascade multiple section using if you have more than 7 product terms in this particular thing you can use it as a feedback example is to form a latch. So lot of you know uses for this particular simple structure which allows us to do many things. So one point about the cascading suppose you have to implement a function which is an OR of 17 product terms some of products there are 17 product terms. So one way of doing is that say in a 16 L8 kind of device is that you implement 7 product terms like 1, 2, 3 up to 7 so you OR it and what you do is that this output comes back here through double inversion and that output is connected to one of the AND gate okay. Then you have 6 product terms because one AND gate is used for cascading then you implement you are left with 6, 7 plus 6 you have 13 we need 4 more so again you take this output bring it back here connect to the next section AND gate and the remaining 4, 4 product terms are programmed in the last section disabled to AND gate and this 16 pin number 16 is a Boolean function some of the 17 product terms okay. But there is a problem with this because if you start look at the input here from this input you have one pass delay come back here then you have second pass delay then come back here you have the third pass delay and if you can imagine if there are some 25 product terms you eat up one more section and you get 4 passes delay and if each passes 5 nanosecond then you have a 20 nanosecond delay. So there is a better way of doing it that is instead of go on chaining like that what you do is that you implement 7 product terms in one section, 7 in second section and this feedback comes here this feedback comes here now this is connected to an AND gate in the third section the second one is connected to an AND gate in the third section. So you have now 7 plus 7, 14 now the remaining 3 product terms you put in the last section and you get 17 product term but if you see the worst case number of passes is 1 like that 2 and 1 and 2 okay. So in a 2 pass you get all kind of all possibilities and if you think of 7 kind of you know AND gates in a section it is possible to cascade 7 such section you know cascaded to an 8 section so you will get 49 product terms in a 2 pass okay. So but if we had gone chaining like that then you have 7, 6, 6 you know take the same number of 8 section then there will be 6 into 7, 42 plus 7, 49 product terms but you see there will be 7 pass delay you know 7 pass delay will be there. So that you should keep in mind when we when the tool cascade it cascaded like that so that is so when you are cascading like if you cascade like 7 plus 6 plus 4 you have 3 passes you have 3 section delay and if you calculate 8 section then you have the first is 7 and the next 6 is you know next 7 you can have 6 product term total 49 product term but there are 8 passes. So you will have lot of delays but if you do 2 pass with 8 section you need only kind of you can still implement 49 product terms 2 passes so the tools when they map the circuit to this they always make sure that it is kind of balance it is always you know like 7 plus 7 goes on and combine in a last section everything together okay depending on the constraints of the number of product terms in each section you know which is available okay. So that is about the cascading then we look at the simple PLDs at least earlier you had something called device called PAL16L8 which we have seen PAL16R4 okay now this is a device which has some registers of flip-flops at the output which allows you to implement sequential circuit and data path mainly counters and finite state machine and 16R8 where all the output has registers and all these are not available now it is it is of kind of academic interest to understand maybe the only device which is being used nowadays and the complex PLDs. So the PAL22V10 is a much more flexible version like which combines all these together you know that is that PAL22V10 we will see that architecture and now the Atmel manufacturers this PAL22V10 still may be useful in very small process like glue logic when you are kind of you want some kind of logic where you know it need to be programmable then you can use that it may be useful because a small amount of logic can be put. And when you look at the simple PLDs the features of the PLDs are it allows wide decoding okay that means that the AND gates of you know 16 inputs and 16 of it complements okay. Now it is very rarely used it is mainly for a chip select decoding of memory and peripherals it was used but many application does not require such wide decoding and in a chip select decoding suppose you have a memory of 1k or 2k then you will use say 10 address lines rest of the address line is decoded as a to map it to appropriate location in the memory space and that is decoded using the chip select decoder okay. So that time this was useful but not anymore so maybe why that is not used if you analyse if you look at the earlier scenario was like this you know you have a microprocessor your peripherals even presently the connect I mean interfacing is similar but earlier the memory of peripheral used to occupy a small address space and you need a chip select decoding. So you have a data bus and a control bus like read bar write bar then some address line depending on whether it is memory or peripheral this could be few or more and chip select decoding will handle the rest of the address line okay. So this is where the one major use of the PAL but now if you look at most of the processors we use are kind of SOCs like embedded processors maybe the desktop processors have some kind of additional chips 1 or 2 or that they are also going into a single chip along with the processor. So they all have the built in memory and peripherals like most of the these have built in memory and peripherals they also have built in configurable chip select decoding. So chip select decoding is part of the SOC that is configurable you can change the address the memory map by configuring it. So there is less use of SPLD like PAL 16L8 okay. So because all these are built in to the single chip and definitely not everything is built in you need some additional peripherals like you say take the case of Wi-Fi many a times that is an external kind of dongle or external peripheral. But they also nowadays whatever external peripherals are working on serial interface okay. So you have a serial clock the processor give a clock and there is a data line which is IO so you can read or write and addressing is part of the data frame that means it is possible to connect multiple peripherals or multiple slaves and this master can address through the data frame okay. And even it is possible to have multiple masters controlling the peripheral and all that. So in this scheme of thing there is hardly any need for a kind of decoding. So that is why these kind of devices are less useful nowadays and that is the effect of kind of large scale integration of the circuit in a single chip. So you must have heard about this SPI or I2C which are serial protocols which is very much used. I am just telling you about why these kind of devices are not found nowadays you know. So what we have seen now you know the beginning part was basically the IO structure which can be used as output input IO it can be used for cascading and when you cascade it you try to do a the tool try to do a two pass cascading than a chaining which will inger lot of delays and you can even form a feedback and we have seen some earlier simple PLDs like 16L8, 16R4, 16R8 and 22V10 which is available now at Mel makes it and why these devices are not much used because the SOCs have built in peripherals memory and built in chip select decoding. And when you use external peripherals many times it has a serial interfacing where addressing is part of the data frame so which kind of you know remove the need of these kind of devices. So let us look at the next device in the line this is called 16R4 as I said this we use it as a stepping stone to understand the later devices okay. So it is pretty much similar so you have 8 sections and or with 7 product terms with OR gate a tri-state enable so here 2 top one is same as 16L8, 2 bottom one is also same as 16L8 but what is different is that in the middle 4 section the output of the ANDR gate goes to a flip-flop okay. And the flip-flops are clocked by a pin, pin number 1 which is a common clock and the output is going through a tri-state gate which is enabled by a pin okay. So this is not of much interest so it can be used if you are connecting to a bus and this can be the control line for reading or writing things like that. So this is hardly of much use so this you can imagine as kind of pass through at least to understand but the important thing to note is that you have some kind of combinational logic proceeding I mean preceding the flip-flop or combinational logic it follows you know followed with the flip-flop that means register and you see the Q bar of the flip-flop is going back to this logic section as input to the AND gate okay. So now that tells you that if you imagine a counter in a counter architecture we have seen we have a next state logic which decode the present state and in a complex counter you will have various input like up, down, load and all that. So it is possible that with this structure now you can have suppose you want to implement a 4 bit counter you can imagine this as Q3, Q2, Q1, Q0 okay. Now all that Q3, Q2, Q1, Q0 and their inversions are here. So if you take this D3 then D3 can be a function of Q3, Q2, Q1, Q0 any function of that you know up to 7 product terms. So it shows that you can implement a 4 bit counter we have to work out the equation for the counter but believe me that as far as a 4 bit counter is concerned it can be implemented okay. You can work out the equation and expand it it is possible to implement a 4 bit binary up counter using this structure because this each section act like a next state logic which decode the present state from various because everything is available and your various input. So that is a next state logic this is the state flip flop which is clocked by a single clock okay. So this allows you to implement a counter. Now okay maybe I will show some pictures of it then you will understand it is even possible that you can implement an FSM okay. If you remember FSM is nothing but a counter with an output decoder okay counter like structure. You have next state logic you have the present state now you know that the FSM what it requires is an output logic which decode the present state and input. Now you take this section where all the present state like q0, q1, q2, q3 is available here. So in principle you can use a form an output which is a decode of the q3, q2, q1, q0 in this and if it is a melee output you know your various inputs you can give input and you can still decode. You have the inputs available because all vertical lines are available here the present states are available here. So it can be you can form an output logic here and you get you can try to implement an FSM okay. What remind you see is a data path, data path is a register then the output of that comes a combinational logic then follow it up with a register. So even a data path in principle can be at least there are hardly any registers here. Suppose you think of an 8 bit it is not possible but I am showing a 1 bit but maybe you can expand it to if there were 8 registers at least you can think of a 4 register followed with some computation in a combinational circuit followed with 4 registers can be done in this structure. So this is an expansion of a pile 16 R4. So as I said there are maximum input 16 because there are say 229 which is 8 plus 1, 4 you know all these are inputs you know so there is 8 plus 8 16 input and registers 4 registers you know that is what the 16 R4 and if you look at each section as 7 product terms or gate common clock the d the or gate output goes to d and q goes as an output and the q bar is fed back it does not matter because both q bar and its inversion is available. So it really does not matter whether you feedback the q bar or the q it is all same you know depending on what you what the device gives the programming changes you know the q the inversion changes that is all about this device. And if you look at a data path as I said we will see how the standard structures map to this particular device. Say take a data path where you have a set of a flops followed with a combinational circuit to the destination register I will just assume that it is a single bit for convenience okay but you can try to expand it to multiple bits. So here you have some inputs you know you can use all these inputs so input is available in this vertical lines here 1, 2 and it is complement 3 and it is complement. Now those input can be one of the input can be connected to the one of the flip flop or a combination of them and you see that output is coming back into this structure this array and that can be you know combined here to form some product terms like a combinational circuit and that goes to the destination register and both get the same clock and you can implement this. And as I said I am just showing one bit but you can imagine if there are 8 registers you know you have 4 registers multiple input you combine them and this structure can be implemented okay. Now if you take an FSM I have already told you there are state flip flops the present state and input is combined in next state logic suppose you take say Q2, Q1, Q0 then this feedback Q2, Q1, Q0 input will form D2, D1, D0 and the same Q2, Q1, Q0 go to some section to generate various output so that is shown here. So you have say I am only showing one bit say the Q0 is fed back here but you can imagine Q1, Q2 and all is available in this array and now you can form D0 as a function of Q2, Q1, Q0 so this is the next state logic this one is the next state logic and that goes to this register. So you have input and the feedback is combined in the next state logic goes to the present state and that present state is decoded along with the input to generate the melee or more output. So this is the next state logic and this is the output logic okay. Of course if there is a flip flop here then you can have a registered output we have discussed why there is a requirement of a registered output when there are glitches in the output due to transitory state then you can have output registering. So that is possible if you use a similar kind of section even for the output then you get automatically the registered output and it does not matter whether you view it like this 3 block diagram or 2 block diagram it is all same like if you view it like that then instead of viewing this next state logic and output logic is separate we can view it as a single logic where part of the logic is used for the next state decoding part of the logic is used as kind of output and that shows you know you have a huge logic section some of it goes to the flip flop some of it goes as output and that is what is shown here you know you have a logic and some of it goes to the flip flop some of it goes direct and this is the same structure you have flip flops feedback into an array that array combines array is logic which combines input and the present state and some goes to the flip flop back some goes at the output exactly same thing you know you have an array where input comes is available here the feedback is available here and some part is used as next state logic which goes to the flip flop and some part is used as output logic which goes as a combination output exactly same thing is so you can say the structure of the pile is like this you know which shows that the pile kind of structure is very useful for finite state machine and counters and things like that but it may not be good as a data path because there are not too many flip flops ok. So one other thing you should know that the advantage of the pile structure is that it has very wide decoding ok and there are lot of product terms available many a times in even we are going to see a practical device where there is more product terms than available in a 16 L8 or 16 R4. So that can be used to kind of reduce the delay I can show you an example suppose you have an output called x a function called x which is ab bar plus cd you have only two product terms and in one pass in a one section you can implement that. Suppose you have a second output which is nothing but y is x plus ef plus gh i so it has already implemented x plus two other product terms. So if you look at it you can say you can implement x here ok and x is fed back here and which can be taken to an AND gate and you implement the next two product terms ok. So that is what is shown here x then ef and gh i so x is implemented here so that is connected to this AND gate then ef and gh i bar is implemented here ok and rest is disabled. So you get y but you know that in that case y will incur a two pass delay like that. So it will be good instead of doing that you substitute this x because after all we have seven product terms you substitute the value of x in the y then y is nothing but ab bar cd plus this. So four product terms so instead of kind of cascading it you copy that whatever product terms here because there are three product terms and you implement the next three here you will get it in one short. So most of the tools used to kind of do that whenever there is a node like that is created it was automatically substituted which uses unused product terms. If unused product terms are there this substitution was done it will reduce the delay ok but this is a problem you know in some cases like take the case of an xor gate see here whatever we have is only an AND or structure. So if you have an xor you have to kind of transform that into a sum of product terms then only you can implement it. It has to be AND or ok so that is the limitation you have no xor gate you have only AND and OR gates everything has to be transformed into SOP form. So if you have ax or b then you will end up with ab bar or ab bar b two product terms but if you have ax or bx or c you can expand that it will become four product terms ok. So if you have up to n product terms ok I have shown I should have given some indexes definitely a to n is not ok but ok I hope you understand that if there are n xor like 1 to n then you have 2 raise to n-1 product terms ok. And you know that the priority engoders adders and subtractors use xor and if you do the substitution business there can be lot of kind of exponential growth of the product terms and it cannot be accommodated like if the tool blindly does it and then start cascading it will waste lot of product terms lot of section and that is not good. So many a times there are attribute to turn off the virtual substitution this substitution business when you have this particular case pathological cases where it goes out of hand the substitution is not a good idea but default most cases the substitution works very nicely other than these special cases you can try to kind of expand maybe the adder equation in terms of the product terms and see how it goes ok. Maybe a 4 bit adder you can try to expand that ok now let us come to the most only available symbol PLD device which is PAL 22V10 this has the same I am only showing half of the PAL 22V10 I cannot show you it is huge so there are instead of 8th section as the name suggests there are 10 outputs so there are 1, 2, 3, 4, 5 exactly a replica mirror image is underneath ok it is a mirror image kind of a flip ok it is a vertical flip of this is down below and you see so there are 10 section and the first thing to notice is that number of product terms are variable ok. The previous devices we have seen that there are 7 product terms but here the top section has 8, 10, 12, 14 and 16 ok and then again back 16, 12, 14, 10, 8 you know so that is how it goes 8, 10, 12, 14, 16 when it comes here it is a lot of product terms ok. Now you see there are 22 inputs that means there are 12 inputs 10 Ios so these are 5 section 5 section is below 10 Ios so that 10 plus 12 is 22 input maximum and these Ios can be used as output so 10 output and this V shows you know tells that it is variable product term ok. Now the next thing is that you have basically a flip flop with some additional circuit ok we will see what is inside there here and it is called a macro cell because it is a more than a flip flop it is a macro which include flip flop and many other things. So you have a clock pin a pin which can be used as a clock for all the macro cell or all the flip flop. Now before even going into the detail of this section I want to say that if you want to use this as a combinational section that means you do not want the AND or output to go to a flip flop and you know register the output of the flip flop you want it directly there is a MUX inside by which you can bypass that flip flop ok. So suppose in some particular application it is a completely combinational application there is no sequential element then you will be bypassing all the macro cell in that case this clock input is a waste. So you can see that that clock is available as an input so if it is not used as a clock it can be used as an input for a combinational input ok. Maybe there is a less use for clock as an input to this array because if you AND the clock with something which in a proper synchronous design may not have much use. So this is given as an input if all the sections are not used as a combinational section ok. So this is a macro cell which includes a flip flop also include a bypass ok. Now you can see that the feedback here it can come from 2 places internally it can come from the flip flop but if you are bypassing the flip flop then that feedback is not useful then this pin is fed back in that case you know like 16L8 it can be used as output input IO cascading all that applies you know. So it is a you can say it is a combination of 16L8 and 16R8 kind of structure everything put together. So that is a kind of advantage of this 22V10 very flexible it combines all those functionalities you do not need an additional device probably that is why this device at least manufacturers are making this device it kind of combine all the advantages of the earlier devices ok. So that is the device and you see similarly you have the tri-state gate and enable by a control product but in addition to this you should note that at the top is an AND gate which can be a kind of decoding of all the 20 inputs or its complement and that goes to the asynchronous reset of the register. So you can in principle say give a reset signal here and you can reset at the power on all the you know all the flip flops and it need not be a simple reset it can be a combination of condition like your multiple condition and depending on those condition you can reset it. Similarly which is not shown in the picture is another AND gate which comes at the bottom of the device at least in the schematic I do not know the real device whether it comes at the bottom but in the picture it comes at the bottom. So that is an AND gate the output of which goes to the synchronous preset of all the flip flops. So if that is 1 then at the next clock all the flip flops all the outputs are set to 1 and here as soon as it is asserted it reset the flip flop ok. So I hope you get an idea of the kind of flexibility of the device a variable product terms 8, 10, 12, 14, 16 and a replica you have 12 dedicated inputs 10 Ios and 10 macro cell the flip flop gets a clock and the macro cell allow bypassing the flip flop and there is a feedback from the flip flop or the combination section there is an AND gate for asynchronous reset there is an AND gate for synchronous reset ok. So now let us look at this macro cell which is shown here that is shown in this part ok. So this is the AND gate which is the top one which is controlling the tri-state gate this is the say if you take the top section so there are 8 product terms OR gate that goes to flip flop and this is the clock this is the asynchronous reset the synchronous set ok. And you see here there is a 4 to 1 MUX ok there are 2 select lines which is pulled up and connected to a fuse ok. So by retaining the fuse both are kind of 00 if you blow one say S0 then you get 01. So by blowing or retaining the fuse you can choose 000011011 so you can choose any of this and you see here you have the possibility of this output or it is complement coming here or the Q or the Q bar coming here ok. So you might wonder why that is required because either you need this output or the registered version of it but this scheme allows some optimisation because suppose you have to implement Y ok is some of product terms now you know that if you have to do that there is an inversion here so one way of doing is that you implement Y and then you select a path like that. So you get the Y you implement Y here ok and it comes like that Y bar and one more inversion you get the Y ok. But assume that say Y when you try to implement you end up with say 12 product terms which cannot be implemented in 8 angies. Suppose you take Y bar it turns out that it is kind of minimised into 7 product terms you apply De Morgan theorem then you end up with 7 product terms so at that time you implement Y bar ok and use this path then Y bar is inverted you get Y. So depending on whether Y is implemented here or Y bar is implemented here you can whichever is less number of product terms you can choose you know if it is Y then take this path Y bar you take this path ok. Same thing applies to the Q and Q bar ok. So this kind of structure allows you kind of a product minimisation ok it is a great thing again nowadays may not be a big thing but at the time of these devices available that kind of saving was very great and you can see them depending on this fuse you can you get a feedback. This is the S1 so if it is kind if it is blown then 1 then these 2 paths are selected that means the flip flop is selected so this is blown then you choose this path you know you choose this path otherwise if it is 0 this particular combination path is chosen. So depending on when you choose these 2 path this is the path goes through the feedback marks when you choose these 2 paths at the output then this is the feedback because so this is like a 16R4. So I hope you understand now the architecture of 22V10 very quickly I want to summarise you have variable product terms asynchronous reset product terms synchronous preset product terms you have combinational or registered output you have product term optimisation by inversion. I am showing an example say this y has 4 product terms and when you take y bar you kind of apply De Morgan's theorem then you end up with 2 product terms and there is a timing maybe we will talk about this timing in the next lecture. So you have propagation delay you have you know output enable and disable timing and the flip flop delay like seat tcq setup and hold time and the reset delay and all that these are the kind of timing parameters in the case of 16L it is just a one section delay there is nothing more to it. So I think here we have looked at the 22V10 the most versatile useful device which is even available today it combines the combinational and the registered part of you know both 16L8 and 16R8 you can use it as a combinational or registered. So you have all possibilities you know you can implement combinational logic you can implement fsm you can implement counter you can even have you know registered output or combinational output for finite seat machine. So it is quite and you have the largest section you have 16 product terms you have reset available preset available. So quite a useful device so this is only simple PLD which is available we will now look I think in the next lectures we can go to the complex PLD having understood this. So I think I stop here this part of the lecture please revise try to understand this architecture well so I wish you all the best and thank you.