 In the previous video we built a couple of D latches. We saw that those were nice because we had control over whether or not we updated the D latch. But they have a drawback to them. As soon as you update that D latch, it's going to change its output. For going to use these memory structures in a clock driven device, then we really need the data coming out of this device to be consistent for the entire clock cycle. In this case we won't want the results of our memory structure to change immediately. We'll want them to stay static until the end of our clock cycle. So this time we're going to be building a D flip flop. It will be constructed from D latches, but it will give us a way to hold on to a single bit of data throughout the entire clock cycle. So our flip flop will have a stable result, even though its internal state will be changing. So I'm going to begin with the D latch. I'll just have a rectangle. And since we saw that the inputs to our D latch won't affect the output to our D latch regardless of whether we're using NAND gates or NOR gates. We're not going to worry about how this D latch is constructed. So I will let this D latch be my input. And it will get a piece of data coming in. And we're going to make this a clock driven device. So I will have a clock signal as well. Clock signal will control when this D latch can update. But as we mentioned, this is only good for half the clock cycle. This will update whenever the clock signal is high, then it would immediately change its results. So we're going to take the results of our D latch and we're actually going to pass them to a second D latch. The result from our first latch will become the data for our second D latch. But instead of sending the same clock signal to our second D latch, we will send the negation of that clock signal. Now this D latch will only update when our clock signal is low. So during the first half of our clock cycle, our clock signal will be high and we can update this D latch. And we get to the second half of our clock cycle. Our clock signal is low. This D latch can update and begin pushing out the new piece of data. That can be used to update some other piece of information, which will be interested in storing its results in one of these entry D latches. But they will have to wait until the clock signal is high to update this D latch. So it will take an entire clock cycle now for our D flip-flop to update and to begin pushing out a new piece of data. That means we don't have to worry about getting inconsistent data during our clock cycle. Our flip-flop as a whole will be nice and consistent, even though we've got these two D latches which are operating out of sync.