 Hello and welcome to this presentation of the STM32WB Analog to Digital Converter Block. It will cover the main features of this block, which is used to convert the external analog voltage-like sensor outputs to digital values for further processing in the digital domain. The analog to digital converters inside STM32 products allow the microcontroller to accept an analog value like a sensor output and convert the signal into the digital domain. There is one ADC and 16 analog inputs depending on the device. The ADC module itself is a 12-bit successive approximation converter with additional over-sampling hardware. Under certain conditions, the over-sampled output can have a 16-bit result. The sampling speed is more than four mega-samples per second. The ADC module integrates three analog watchdogs. The data can be made available either through DMA movement or interrupts. This ADC is designed for low power and high performance. There are a number of triggering mechanisms and the data management can be configured to minimize the CPU workload. One analog to digital converter is integrated inside STM32WB products. The input channel is connected to up to 16 GPIO channels capable of converting signals in either single-end or differential mode. The ADCs can convert signals in excess of five mega-samples per second. There are several functional modes which will be explained later. There are also several different triggering methods. In order to offload the CPU, the ADC has three analog watchdogs for monitoring thresholds. The ADC also offers over-sampling to extend the number of bits presented in the final conversion value. For power-sensitive applications, the ADC offers a number of low-power features. This slide shows the general block diagram for the analog to digital converters embedded in the STM32WB microcontroller. The STM32WB's ADCs support a deep power-down mode. When the ADC is not used, it can be disconnected by a power switch to further reduce the leakage current. Auto-delayed mode makes the ADC wait until the last conversion data is read before starting the next conversion. This avoids unnecessary conversions and thus reduces power consumption. The power consumption is in function of the sampling frequency. For low-sampling rates, the current consumption is reduced almost proportionally. The ADC supports up to 4.27 mega-samples per second of conversion. The ADC includes the over-sampling hardware which accumulates data and then divides without CPU help. The over-sampler can accommodate from two to 256 times samples and right-shift from one to eight binary digits. The sequencer allows the user to convert up to 16 channels in any desired order. Also, each channel can have a different sampling period. The ADC offers an auto-calibration mechanism. It is recommended to run the calibration on the application if the reference voltage changes more than 10%, so this would include emerging from reset or from a low power state where the analog voltage supply has been removed and reinstated. The ADC needs a minimum of 2.5 clock cycles for the sampling and 12.5 clock cycles for conversion. With a 64 MHz ADC clock, it can achieve 4.27 mega-samples per second. For higher-speed sampling, it is possible to reduce the resolution down to 6 bits, then the sampling speed can go up to 7.11 mega-samples per second. The sampling time can be programmed individually for each input channel of the analog to digital converters. The sampling times listed in this slide in ADC clock cycles are available. Longer sample times ensure that signals having a higher impedance are correctly converted. The ADCs have a selectable clock source. When the system needs to run synchronously, the AHB clock source is the best selection. If a slow CPU speed is required but the ADC needs a higher sampling rate, the dedicated ADC clock can be selected. AD converter supports several conversion modes. Single mode, which converts only one channel in single shot or continuous mode. Scan mode, which converts a complete set of predefined program input channels in single shot or continuous mode. Discontinuous mode converts only a single channel at each trigger signal from the list of predefined program input channels. The ADCs support hardware over sampling. They can sample by 2, 4, 8, 16, 32, 64, 128 and 256 times without CPU support. The converted data is accumulated in a register and the output can be processed by the data shifter and the truncator. 12-bit data can be extended to be presented as 16-bit data. This functionality can be used as an averaging function or for data rate reduction and signal-to-noise ratio improvement as well as for basic filtering. Each ADC has three integrated analog watchdogs with high and low threshold settings. The ADC conversion value is compared to this window threshold. If the result exceeds the threshold, an interrupt or external signal can be generated or a timer can be immediately stopped without CPU intervention. The ADC conversion result is stored in a 16-bit data register. The system can use CPU polling, interrupts or DMA to make use of the conversion data. An overrun flag can be generated if data is not read before the next conversion data is ready. For injected channel conversions, four dedicated data registers are available. An injected conversion is used to interrupt the regular conversion then insert up to four channel conversions. Once an injected conversion is finished, the regular conversion sequence can be resumed. The injected conversion result is stored in dedicated data registers. Flags and interrupts are available for the end of conversion or end of sequence. The choices for an injected channel can be reprogrammed on the fly. Even if a regular or injected conversion is in progress, you can add a different channel to the queue so that the next injected channel can be different from the previous one. Each ADC can generate nine different interrupts. ADC ready, end of conversion, end of sequence, end of injected conversion, end of injected sequence, analog watchdog, end of sampling, data overrun and the overflow of the injected sequence context queue. DMA requests can be generated at each end of conversion when the ADC output data is ready. The ADCs are active in run, sleep, low power run and low power sleep modes. In stop zero, stop one or stop two mode, the ADCs are not available but the contents of their registers are kept. In standby or shutdown mode, the ADCs are powered down and must be re-initialized when returning to a higher power state. There is a deep power down mode in each ADC itself which reduces leakage by turning off an on-chip power switch. This is the recommended mode whenever an ADC is not used. The following table shows performance parameters for the ADC. These peripherals may need to be specifically configured for correct use with the ADCs. Please refer to the corresponding peripheral training modules for more information. Several application notes dedicated to analog to digital converters are available. To learn more about ADCs, you can visit a wide range of web pages discussing successive approximation analog to digital converters.