 Hello and welcome to this presentation of the STM32MP1 USB Full Speed and High Speed Interfaces. It covers all the features of these interfaces which are widely used to connect either a PC or a USB device to the microcontroller. This figure shows the connections between an STM32MP1 microcontroller and two USB connectors. The STM32MP1 features a two-port USB high speed communication interface allowing the microcontroller to communicate, for example, with two USB storage devices. Let's look at some of the key features of this USB high speed interface, which is a USB specification 2.0 compliant interface that operates at 480 megabits per second bitrate. A USB 2.0 high speed PHY is integrated on chip avoiding the need for external ULPI transceivers. Built-in support for linked power management adds enhanced power modes on top of the USB 2.0 specification. The battery charger detection function allows for increased current to be drawn from BC 1.2 compliant chargers up to 1.5 amps. In this block diagram, the USB OTG host controller core is shown at the top. It can be used with both ports of the HS or high speed PHY. If desired, the second port can be controlled by the OTG controller, which also has unique access to the FS or full speed PHY. These PHYs on its right side handle the analog signal levels, including many specific level detections relating to on-the-go and battery charger detection functions. The USB interrupt goes to the Cortex processor to signal various USB events. The AHB slave interface enables read-write access of the controller registers and the power and clock control block. Transfers to and from memory are handled by a DMA engine inside the controller via the AHB master interface. At any given time, one of the two operating modes will be functional. Peripheral mode, which will be used for a regular device or an OTG device when operating in peripheral mode. Or targeted host mode, which will be used for an embedded host or an OTG device when operating in host mode. Interrupts from this USB block can be triggered by a large number of events or state changes. This slide shows all the events that can trigger an interrupt. As can be seen, these interrupt sources are diverse events. Low power modes for the high speed core are similar to the full speed. But the modes concerning the PHY are not listed, as in this case the PHY or transceiver is an external component. The USB H controller is fully active in run mode. During USB suspend, sleep, stop and LP stop modes may be used. USB PHY-C is a small controller needed whenever the high speed PHY will be used. It is to be used for controlling the PLL inside the high speed PHY and enabling the USB H controller access to its second port. Fine tuning of the high speed PHY should also be done by using USB PHY-C. This is necessary to get notably a well-adjusted eye diagram. Here is an application example of a low power device. Power is drawn directly from the USB Vibus signal. A single crystal oscillator starting from 4 MHz is needed outside. For complete USB specification documents, please refer to usb.org. The USB 2.0 document homepage has a zip file containing the USB 2.0 and OTG 2.0 specifications and an ECN for LPM. The USB device class documents page has the battery charger specification.