 I will come back to this diagram in a while. This is a recent result by Ryan Williams which I will talk about. It shows a lower bond on the class ACC. It is a fairly simple result on hindsight. It took quite a while for even this result to be proven. So, clearly it is it was not obvious at all in the beginning. And here is the overview. I will just first give you some background about what all I will talking about and then show you the proof of the lower bond. So, let us start with some basics. And as I said it is a very simple result and I have one hour to speak and to fill that up I will give you all the basic definitions. So, even though you may know it. So, circuits are sequence of Boolean operations. Each operation is also called a gate and these are applied on Boolean inputs. Typical of these operations are and or and not. These are the most common ones, but there are some others in particular in this talk I will consider two more kind of Boolean operations. The first is the first one is mod k which is a gate which takes in a bunch of inputs sums them up and outputs a one if and only if some of the inputs equals 0 modulo k otherwise your outputs are 0. And the other is a symmetric gate which I just call it same. It represents some symmetric function of the inputs which in turn means that it only the output only depends on the number of ones in the input. So, depending on the number of ones it may output 1 or 0. And of course, the circuit does something useful. So, it produces some output bits which is called the output of the circuit. And then we have this notion of circuit complexity which is determined by certain parameters associated with the circuit. The most important one of them is size which is the number of gates in a circuit. And second most one is depth which is the largest the length of the largest path from an input to an output. And finally, the circuit complexity of a Boolean function which is computed by can be computed by different circuits is the size of the smallest circuit which computes this Boolean function. Now, circuit is defined on a fixed number of input bits it has a fixed size. Now, if you want to use circuits to classify sets which are infinite objects. So, we need to use an infinite family of circuits one for each input size. So, each for a particular input size the corresponding circuit accepts or rejects or determines membership of strings of that size in the set. And there is this notion of uniformity now which comes into play. And this is that given in such an infinite family of circuits if you consider the problem of generating a circuit from this family. Well, if let us read that as if there is an efficient algorithm now the notion of efficiency here changes from the context. But we will just leave it at this if there is an efficient algorithm which on input n produces the circuit in the given family which works on an input size. Then the circuit family is called uniform. So, there is a uniform way of going from an input size to the corresponding circuit of the family otherwise the circuit family is called non-uniform. And these two notions will be crucial or important in this talk. Okay. Now, using circuits we can or rather infinite family of circuits we can now define classes of sets. The most important one in terms of circuits is the class P which is precisely the class of all sets accepted by uniform polynomial size circuit families. So, that is an alternative characterization of the class P. The advantage of using circuits to define classes is that we can define subclasses of P and that is where these are mostly used. Now, because the size parameter is something we cannot do much with we have to have polynomial size circuits just to read in inputs we have to have some certain number of gates. But we can vary the other parameter which is depth to define subclasses. So, NC is the class of sets accepted by polynomial size and polylog depth circuits. And we can go further down define ACK is the class of sets accepted by polynomial size constant depth circuit families. And the gates in this circuit are of a special kind so far in these P and NC we I am just assuming and or and not gates of the standard kind. And in ACK I am introducing gates of different kinds likely. First of all, ands and ors are present in ACK but they have unbounded fan in rather they have allowed to have unbounded fan in and then mod k gates. So, ACK fixes the k and then we allowed to have mod k gates as well. And the class ACC which is the class of central interest in this talk is the union of the ACK overall case. We have a smaller class than ACC also which is AC0 then that is the class of sets accepted by polynomial size constant depth circuit families in which unbounded fan in and and or gates are allowed no mod k gates only a not gate allowed. This in a sense is the smallest sensible class of circuits cause yeah class of sets define using circuits. And it is obvious to see that AC0 is contained in ACC which in turn is contained in NC which in turn is contained in P. Now the one of the reasons to define these small circuit classes was that we can prove lower bounds on certain number of them. Quite a while ago a whole bunch of authors showed a whole bunch of lower bounds on the class AC0 and they essentially all say that this function mod 2 which is the parity function requires super polynomial sized non-uniform AC0 circuits. Then we had some extensions of this lower bound. Rosborough in 87 showed that mod 3 which is this function which takes some of its inputs and outputs a 1 if and only if the number or the number of 1s is divisible by 3. Mod 3 requires super polynomial size non-uniform AC2 circuits. So this is an extension of this because we are now allowing mod 2 gates also in this. And this was further extended by Smolensky who showed that in general mod q function requires super polynomial size non-uniform ACP circuits for all distinct primes and I would like you to notice the year here that is 1987. Then a slightly different direction, Elendor and Gore showed that permanent required super polynomial size uniform ACC circuits. I am actually reducing the strength of their result here they showed it for a slightly bigger class than ACC here. But since we are talking about ACC I am writing it this way. So this is a lower bound on ACC however it is only on uniform ACC circuits not on non-uniform ACC circuits. And there may be a huge difference between uniform ACC circuit and non-uniform ACC circuits because the non-uniform ACC circuit one can even recognize undecidable states. And so in about 6 years period starting from 81 to 87 all of these lower bounds came which gave rise to a lot of hope among complexity theories that we can use the circuit model and extend the techniques we have we developed to show bigger and bigger lower bounds eventually aiming for P0 equal to NP or showing that a problem in NP requires super polynomial sized circuits. However that was not to be after 87 all progress on proving lower bound for non-uniform circuit classes start. There were explanations for that but I am I will not get into that. And until very recently therefore it was not even known if the class NEXP which is the class of sets accepted by non-deterministic Turing machines working in exponential time. Even if there is a this is bigger than non-uniform ACC class that is not all sets in NEXP can be recognized by polynomial sized ACC circuits. And this was until recently because now just last year Fran Williams showed that NEXP required super polynomial sized non-uniform ACC circuits. Now we come to this figure to show this gives you a glimpse of what we are talking about this is the class NEXP which inside which sets EXP inside which P space NP P NC and there is this tiny dot which is ACC. And even this is a misrepresentation because these classes are actually much bigger. So what one is really this result is really saying is that this small really tiny class is not equal to this big class which is not saying much on one hand because this clearly is not very impressive. But on the other hand given the fact that even this seemingly non-impressive task we could not perform for 24 years and some real cleverness was required to prove even this result it is an achievement that we have made at least some progress now. Okay so here is the outline of the proof it consists of a sequence of four lemmas. Okay before I give you the lemmas I will give you some definitions by the way I should go back here and from now onwards whenever I say ACC it is implicitly assumed that it I am talking about non-inform ACC circuits because that is what the result is about. Some definitions which are important for the proof for a circuit C which has N inputs let us denote by D of C to be the 3 set instance which is encoded by the 2 to the N bit characteristic strings of C. What I mean here is that take the circuit C it has N inputs evaluate the circuit on all 2 to the N distinct inputs in some order and so you get 2 to the N bits of output and just concatenate them as in a 1 2 to the N bit long string. Think of that string as coding a 3 set formula and that is the formula D of C this can be also viewed as saying that circuit C is a very succinct representation of a large 3 set formula and that what gives rise to this names succinct 3 set is the set of circuit C such that D of C is satisfiable. So, succinct C is a very has very succinctly represented satisfiable 3 set formulas that is the second definition. There is another class of satisfiable formulas I am defining this is ACC set is the set of all ACC circuits that are satisfiable. So, here I am viewing an ACC circuit as just representing a satisfiability problem that is is there a an input on which this ACC circuit outputs a 1. So, ACC set is the set of all satisfiable ACC circuits and finally the class NE which is a subclass of NEXP is the class of sets accepted in time non determinist by non deterministic 2 to the order N time curing machines. So, here are the 4 steps earlier promised first one and this is a really an old step with the same follows from the Cook-Levin proof of NP completeness of 3 set that succinct 3 set is NEXP complete this complex contains very succinctly represented 3 set formulas. So, you would expect it is complexity to be much bigger than 3 set and it is NEXP complete. Step 2 again this is a result shown while ago by Pagliazo, Carbonats and Witterson. This says that if NEXP is contained in ACC then for every set in NE which is a slightly smaller subclass of NEXP not much smaller than for every set L in NE for every string X belonging to this set L of length N there exists a circuit W sub X of polynomial size such that D of WX. So, D of WX is that expanded 2 to the N bit characteristic vector is a satisfying assignment to D of CX. Now, I should explain here a bit that see L is in NE succinct set is NEXP complete. So, there is a polynomial time reduction from L to succinct set. Let X to C sub X be the reduction of L to succinct set succinct 3 set. So, CX is a polynomial sized circuit this represents a succinctly represents a 3 set formula and D of C sub X is that 3 set formula. If X is in L then this of formula is satisfiable. If this formula is satisfiable then it has a satisfying assignment and what this lemma is saying is that that is there is a one satisfying assignment to this formula which can also be succinctly represented and it is represented by the circuit W sub X. That sub then the length of that satisfiable satisfying assignment is exponential in N, but the size of W sub X is polynomial. So, this circuit very small circuit W sub X succinctly represents a satisfying assignment to this succinctly represented 3 set formula. So, this lemma essentially says that if there is a 3 set formula which is succinctly representable then there is a corresponding satisfying assignment if that 3 set formula is satisfiable which is also succinctly representable. However, under the assumption that NEXP is contained in ACC not otherwise. So, in the next two lemmas were proved by Ryan Williams. So, third one which is the first one of the Ryan Williams lemma is that if ACC side which is recall is the problem of given an ACC circuit to check if it is satisfiable. So, this can be if it can be solved in time 2 to the N minus omega log N. So, this is slightly better than brute force if you are given an let us say ACC circuit on N inputs well you just try out 2 to the N this all inputs and check evaluate the circuit on each one of them that is exponential time algorithm to check if the circuit is satisfiable. If you can do it slightly better than that in this fashion then NEXP is not contained in ACC. And the final lemma is that ACC side indeed has an satisfying algorithm or algorithm of this time complexity. So, put these two together you get NEXP is not contained in ACC one might wonder what is the reason for these two lemmas well to prove this lemma we need both of these. So, let us get into the proof the first lemma it is really straight forward you just look at the standard reduction of any non-deterministic Turing machine to a 3-side formula that. So, you take an L in NEXP and taken instance X and consider that exponential time 3-side formula that is satisfiable if and only the X is in help. Now, that has such strong regularity in it and if you think about it for a moment you will realize it that it can be actually compressed into a small size circuit. So, one can actually construct given X in polynomial time one can construct this small circuit C sub X whose characteristic string is this large 3-side formula and that is it. So, that shows that succinct 3-side is NEXP complete let us go on to the second lemma which was the Pugliazo-Cobanets-Whitterson result that if there is a succinctly represented 3-side formula then it has a succinctly represented satisfying assignment provided it has one and provided NEXP is contained in ACC. So, let us assume that NEXP is contained in ACC and the suppose this is that the conclusion is not true which means there is a set L in NE such that there are infinitely many X's in L for which no W sub X of polynomial size exists right. So, that is a contra positive. So, collect all such X's in a set which I am calling S so you get an infinite set of strings S and the I am naming the strings in this by X sub J K's such that all these strings belong to L because otherwise satisfying assignment does not exist and just a more clear writing of this statement no W sub X of polynomial size exists here it is saying that for all D for all large in F K for all Y which of length at most 2 to these exponential in size essentially in length of X J K if Y is an accepting path for X J K which means that in the see this is a N L NE machine. So, there is an exponential time accepting path for NEX in L see Y then codes an accepting path for this then the circuit complexity of the function represented by Y is more than this see W sub X is a circuit representing a satisfying assignment. Now, this satisfying assignment of this formula can be also be extracted very easily from Y which is a satisfying path for the string X sub J K because there is a polynomial time reduction from L to succinct reset. So, the fact that there is no such W X means that any Y which is an accepting path for the string cannot be compressed to a small size circuit and that is what this is saying that the circuit complexity of this Boolean function is exponentially long string so think of it as a Boolean function and that Boolean function has large circuit complexity and the moment we view it this way we can do interesting things with it because the this Y is are now hard functions which we get not quite for free, but we do get them through X J K's X J K's are small and these Y's which are accepting paths for X J K's are hard functions. So, the strings therefore in S in some sense represent hard to compute function not directly but implicitly and we use this you know using this standard hardness versus randomness tradeoff we will use these hard to compute functions to de-randomize MA in the following way. Take a set A in MA and run the following algorithm on an input of size N Arthur is a polynomial time machine so there is we can represent Arthur by a circuit of size say N to the A fix a small epsilon and consider N which is X sub J K to the 1 over epsilon A so take only those ends which have for some X J K this size. Now, for this algorithm I will take X J K as an advice given this as an advice guess an accepting path for X J K say Y and verify that it is an accepting path that is an exponential non-deterministic exponential time verification. So, the time taken is 2 to the order N to the epsilon AC and it is non-deterministic. Once you have made this guess and got this Y which is recall is a hard to compute function also guess Merlin's communication to Arthur say alpha Merlin only sends one string to the Arthur because it is a MA protocol and this is takes small time non-deterministic polynomial time. Now, use Y as a hard to compute function to construct a pseudo random generator which maps seats of size N to the epsilon A to output of size N to the A this we can do easily using standard techniques. Now, given this pseudo random generator you generate for all possible seats they all possible inputs and evaluate Arthur circuit on Merlin's communication alpha and all these outputs of the generator. Arthur is a circuit with some random inputs which is random coin tosses and Merlin's information and the input. So, Merlin's information is alpha input is already fixed the random part of the Arthur's computation is provided by this pseudo random generator and try it out on all the seats. Since, I am trying out in all the seats that stood the end to the epsilon A and there is the C also somewhere coming because of the time complexity so that is the time complexity and except if an only majority of these computations except. Now, if Y is indeed a appropriately hard function then this will work correctly and Y is certainly hard function by our assumption. So, that proves the correctness of this algorithm. Now, let us look at the time complexity well the time complexity is simply just add everything up it is a non deterministic algorithm running in time 2 to the order N to the epsilon AC and now epsilon was arbitrary. So, I will choose epsilon to be some delta over AC and this we get that M A infinitely often is in time in can be solved in non deterministic time 2 to the n to the delta with an n to the delta size advice. The advice is the string x jk and the time just comes out in this and it is infinitely often because only for x jk is our appropriate length where that we can solve it. So, it is only infinitely often. Now, use the fact that any x p is contained in ACC which of course, ACC is certainly contained in polynomial size circuit which means that any is contained in a fixed size time complexity or fixed size circuits because and that is the reason for choosing any not any x p any is if any x p is contained in ACC then there is a take a complete problem for any likely succinct side is probably complete for any also. So, that will have a fixed size ACC circuit all sets in any linear time reduced to this complete problem and so, they all have the same fixed size circuit up to a constant multiplier. So, any is contained in this and m a is surely contained in any therefore, m a is infinitely often contained in this is essentially circuits of size n to the q again use the fact that this time x e x p is contained in ACC and invoke a classical result that if a x p is in p slash poly then e x p equals m a. So, this gives us that e x p equals m a. So, just plug this in and you get e x p is infinitely often contained in fixed polynomial size circuit and that is impossible we can just diagonalize against this. So, there is a class standard time hierarchy theorem shows that e x p can not be infinitely often contained in fixed size or fixed exponent size circuits. So, that establishes this level this is what we knew certainly from 2002 and now comes the new ideas of Ryan the third lemma it says that if ACC sat can be solved in slightly better than brute force time then any x p is not contained in ACC. So, we will again derive a contradiction by assuming that ACC sat can be solved as this in this time and any any x p is contained in ACC. So, how does it go? Again let us start with some set L in any and we will as you would expect we will this time contradict another time hierarchy theorem actually non deterministic time hierarchy theorem. So, we will eventually derive an algorithm for L which will solve in less than exponential time. So, to do this we design two algorithms the first one thus something which was almost already guaranteed by the previous lemma. So, this algorithm which I am calling script A on input x outputs a circuit c prime sub x such that x is in L if and only if c prime sub x is in succinct sat and c prime sub x is an ACC circuit. Now, this if you remove the second clause this is already given by the first lemma by the fact that succinct 3 sat is an any x p complete. The key thing here is that this I am saying that this circuit is not just a any polynomial size circuit this is actually an ACC circuit. So, how does the algorithm A work? So, this is really clever. Take input x of size n first step compute c sub x that is a polynomial time reduction gives you a polynomial size circuit with the required properties. Now, I want to compute an ACC circuit which is equivalent to c sub x. So, to do that I will guess an ACC circuit say d which on input x comma j outputs details of jth gate of c sub x and this will also be small polynomial size circuit. So, guess is polynomial size the ACC circuit d which takes as input x comma j and produces all the details of the jth gate of c sub x. Now, why what is the guarantee that such a d exists? Now, at this point I did not account for the fact that I will not have access to my laptop here. So, I need to click on this. Okay, let us let us not worry about it. Let me try to convince you that such a d will exist it is actually fairly simple. Let us not worry about ACC ness of d first of all you are are you convinced that if there exists a polynomial size circuit d which will do this c sub x is itself polynomial size it can be computed in polynomial time. So, there is surely a circuit. So, this is like a uniform t machine from x it produces c sub x. So, there is clearly another circuit which is polynomial size which will produce all the connections or all the descriptions of the gates of the circuit c sub x that is a now use the fact that any x p is contained in ACC which of course means that p is contained in ACC. So, all polynomial time computations can actually be done by polynomial size ACC circuit. So, this is a one particular polynomial time computation which produces all these connections which can be done by ACC circuit. So, there exists therefore, a polynomial size circuit ACC circuit d which does the job. Once you guess this then verify that d is correct and again why that is very simple just compare all generate all the outputs of d and c check because c x is already generated and check if all the gates are predicted correctly. And the reason why you need to guess ACC circuit d is because we have only know that p is contained in non-uniform ACC. So, there exists a polynomial size ACC circuit which does this, but we would not be able to compute it. So, that is why we guess it. So, let us continue with this algorithm we have the circuit d. Now, this algorithm guesses another circuit e which is also an ACC circuit and this circuit d behaves as follows on input i, j it computes the output of the jth gate of c sub x on input i. So, d was computing all the connections of circuit c sub x and e is computing all the outputs of all the gates of c sub x. This is also small size polynomial size circuit. So, it takes time polynomial in end to guess it and to convince you that such a circuit e exists I will use the same argument. Since c sub x is polynomial size there exists a polynomial size circuit which does the job. If that polynomial size circuit we can simply simulate c sub x on input i and produce a corresponding output. Now, again invoke the fact that p is contained in non-uniform ACC to conclude that there exists an ACC circuit e which does. So, we have the circuit d and e. Now, define this predicate value i j this is 0 if and only if e i j is the right output of the gate j of c c x on input i of course, when this gate is fed inputs e i comma j 1 and e i comma j 2 where j 1 and j 2 are gates providing input to gate j as per d. That is in English let me try to explain it. So, see the fundamental problem here is that d is verified to be correct it produces what it should be. How do you verify that e is doing what it should? One way is to know run evaluate c sub x on all inputs collect all those output values and then check run e on all inputs and verify, but that is too much that takes exponential time we do not have that much time. So, we will do that cleverly and the way we do it is we focus on one particular gate say jth gate use d to generate that all the description of that gate that this is the gate say and gate it gets inputs from gate j 1 and j 2 let us say fine once d gives all this information which we know is correct information then we evaluate e we run e on j 1 on j 2 and on j. So, if e was correct on j 1 and j 2 we can verify the correctness of e on j. So, it is some sort of an inductive verification okay and the way we define this predicate is that it takes value 0 if it is correct that is the output of e j is correct assuming e j 1 e j 2 was correct. Now, this predicate in itself is computed by an HCC circuit why that is pretty simple just on this input first run d which is an HCC circuit d produces gate j description of gate j description of j 1 description of j 2 then run e on j 1 e on j 2 and e on j. So, the three parallel executions each is an HCC circuit and then some do some computation on the top. So, it is an HCC circuit. Now, since this is computed this predicate is computed by an HCC circuit use the HCC SAT algorithm that we have at our disposal to check the satisfiability of this predicate and check the satisfiability of value using HCC SAT algorithm and the time it takes is this much by assumption and now comes the key thing that if value this predicate is unsatisfiable then the out is correct essentially because value is satisfiable if and only if at every location the that is value output 0 everywhere which means every local computation done by circuit e is correct and therefore, the global computation by circuit e is correct. So, once we have verified that e is correct by circuit c prime sub x which was a goal of algorithm a is simply the circuit e it is value at the output gate e produces the value of c sub x at all the gates. So, just pick up the output gate ok. So, I do not need to click on this. So, I have convinced you hopefully that it is correct. Therefore, you conclude that we have a non deterministic algorithm script a run whose time complexity is this and which computes c prime sub x which is an HCC circuit which is equivalent to c sub x ok. So, the proof is not done because we have just one algorithm there is no contradiction yet contradiction comes now. Let us define another algorithm b which will accept this set L which we picked from the class n e. So, what the algorithm b does is on input x of size n first runs a to generate c prime x and that is the time complexity. Next is guesses an HCC circuit w prime sub x which quotes a satisfying assignment of this 3 set formula. We know by the previous lemma that since any x p is contained in HCC there exists this polynomial size circuit w sub x which quotes a satisfying assignment. And use the whole the same argument which that because p is contained in HCC. So, this polynomial size circuit there is an for this polynomial size circuit there is an equivalent HCC circuit doing the same job. So, there exist a such a circuit w prime sub x in HCC which quotes a satisfying assignment. So, we just guess it we cannot compute it we guess it. The moment we guess it we need to verify that it is indeed because if we unless we verify that this is correct we have no way to proceed. So, how do we verify that w prime sub x is correct we do the same thing as we did last just now. We define another predicate which will verify that this w prime sub x is correct. So, we construct an HCC circuit F to verify the correctness of w prime sub x. What this circuit does is it takes. So, what is w prime sub x supposed to do it takes a variable and outputs a satisfying assignment or its value that should be present in the satisfying okay. So, the circuit F first uses C prime sub x what does C prime sub x do? C prime sub x generates that 3 set formula. So, I pick now 3 set formula is a conjunction of clauses each clause has 3 variables. So, I use C prime sub x to pick one of these clauses and I will do it once for each clause. So, pick one of the clauses of this 3 set formula. Once the clauses are picked I know the what are the variable numbers occurring in that clause. I use w prime sub x to find assignment to those 3 variables and the circuit F should accept if and only if this clause is not satisfied by this assignment given by w prime sub x. So, this is again a local computation it says that except if and only if or except if and only if the clause is not satisfied locally that particular clause by this particular assignment. And now this is an HCC circuit we can test the satisfiability of this HCC circuit by the algorithm we have at our disposal and again it is clear that F is unsatisfiable if and only if w prime sub x is correct satisfying sign because F is unsatisfiable means every clause is satisfied by w prime sub x. So, it takes time this once again. So, just put everything together. So, the algorithm B is a non-deterministic algorithm which generates or very you know guesses the w prime sub x and checks if it is correct and the time it takes is this much. Now, the moment we have w prime sub x what do we know? We know that x is in L w prime x sub x is a satisfying assignment to the 3-side clause here. So, which clearly means by the reduction of L to succinct 3-side that x is in L. So, the algorithm B can simply accept it this time. So, here is an algorithm for L in any which works in time 2 to the n minus omega log n and this contradicts a non-deterministic time hierarchy theorem. If there is a better than brute force algorithm for ACC sat then we have a lower bound and finally we show that we indeed have a better than brute force algorithm for ACC sat. Good. So, we are given a circuit C now which is an ACC circuit of depth D and polynomial size on an inputs and we want to test its satisfiability that is there in input assignment on which this outputs a bottom. So, first we do a minor surgery on this circuit as we will see we will want to shrink the number of inputs to something smaller from n. So, what we do is define another circuit C prime which is an or of 2 to the L copies of C such that in each copy the first L bits of input are set to a unique value. So, take the first L bits they are 2 to the L distinct values it can take set them to each one of these value we get 2 to the L copies take their order. Clearly C prime is satisfiable if and only if C is satisfiable size of C prime has grown 2 to the L times polynomial size now depth has grown up by 1 and we will fix L later the key thing here to note is that the number of inputs is n minus L now. Now, we use one of the another earlier result it was done again in 80s well not quite 80s 90s actually which and this is the only place we are using specific property of ACC circuits until now everything I proved can in which I can replace ACC by just about any other circuit class and that will go through. The circuits in ACC have a very special property and that is what is going to be exploited now. So, any circuit ACC circuit C prime can be replaced by an equivalent circuit D with the following properties D has depth 2 does not matter what depth C prime has G has only depth 2 with a symmetric gate S at the top and AND gates below. So, it is a symmetric gate and ANDs gate in the level for bottom level that is it there are you know there are no NOT gates also here just AND gates working on the N inputs. The size of D grows C prime was polynomial size this is or C was size 2 to the L times P of poly in it and this becomes essentially 2 to the order poly log N which is now because of the size is 2 to the order L to the E log to the E and for some constant E this constant is determined by the depth. So, this is where the depth is reflected further this circuit D can be computed reasonably efficiently from C in this time that is the whatever time whatever the size of D is in roughly that same time I can compute D from C prime sorry not from C and further the symmetric gate at top is not a very complex symmetric gate it is it can be evaluated in roughly the same time that is the number of inputs it has roughly the same time it requires to be computed ok. Now, we choose L set L to N to the 1 over 2 E. So, just work out the numbers what we said it is the D has size order 2 to the N to the 2 thirds and let that be represented by capital U and all the evaluation times that this computation time this evaluation time similarly bounded and moreover the number of inputs to D is N minus N to the 1 over 2 E which I am going to represent for the moment by N. So, D has M inputs and size capital U now I want to evaluate this D. So, I have this I started with C prime I did this translation in reasonable time to this circuit D the goal is to check if D is satisfiable how do I check D is satisfiable D has a very simple structure is a symmetric gate and gates at the bottom. So, now, I will exploit the fact that there is a symmetric gate sitting at the top and symmetric gate symmetric gates output only depends on number of ones in the input we work first there are M inputs now to this gate. So, I can number the inputs 1 to M and let this set this is a set 1 to M take any subset S of this and let F of S equal the number of AND gates in the circuit D with precisely the variables in S as input. So, S denotes a subset of input variables and F of S denotes the number of AND gates in the circuit with precisely these variables F of S can be computed for all S in time order U there are order U AND gates. So, just go through each AND gate and update the appropriate value of F corresponding F of S. Now, define another function G of T again being a subset of variables and G of T is defined to be this sum sum S contained in T of F of S this the idea of defining this is that G of T is precisely the number of AND gates of D that output a 1 when exactly the variables in the set T are set to 1 right if you set the variables in set T to 1 all the AND gates which take subsets of those are set to 1 and that is this number G of T. So, there are 2 to the M distinct values of set capital T and for each one of them G of T will give the number of AND gates which are set to 1 which is the number of 1's which are fed to the symmetric gate and that is a key thing that we are interested. Now, there is a simple trick it is actually to compute G of T you can use it computed using dynamic programming instead of directly trying to do the sum here is the formula I will not explain this you can work it out very easily if you define G 0 T to be F of T and G i T to be G i minus 1 T plus G i minus 1 bracket T subtracted with i if i is contained in T otherwise G i minus 1 T then it is easy to see that G of T is same as G n of T and just using this formula you can see that it can be computed in time order 2 to the M times M. So, we can compute G of T also very in time order 2 to the M times M and F of S can be computed in order u time. Okay I have mentioned this again and this is again reiterating the fact that the symmetric gate value depends only on the number of 1's which are fed to it how many 1's are how many lines are going into the symmetric gate u lines at the most u is the size of the circuit. So, there are only u values u distinct values on which we need to compute the output of the symmetric gate. So, G of T is therefore we will take at most u distinct values there are 2 to the M G of T is what they will take on u distinct values. So, all we need to do is for each value of G of T check evaluate the symmetric gate on that value and see if it outputs a 1 each evaluation of the symmetric gate by our assumption takes order u time there are order u such u distinct value. So, order u's in order u square time we can check if the symmetric gate outputs a 1 on any of the G T's which is the goal that will do the satisfiability. So, the algorithm does all of this and the overall time complexity is ordered u square plus 2 to the M times M and just plug in the value of u which was 2 to the N to the 2 thirds and M was N minus N to the 1 over 2e plug in that value you get this and well this is all bounded by this 2 to the N minus omega naught completes the entire proof. So, some final comments that the first of all the only place ACC property was used in this fourth step where we replaced an ACC circuit by this special circuit which has a symmetric gate and AND gates at the bottom. And so, if we can do something similar or something different also, but all we need to do is to find a slightly better satisfiability algorithm for any circuit class. If you can do that we get the NXP not sorry it should be not contained in that circuit class. So, that is one take away from this take any circuit class find a slightly non-trivial satisfiability algorithm for that circuit class you get any XP is not contained in that circuit class. For ACC we use that special property of ACC to derive this non-trivial satisfiability algorithm for others bigger classes than ACC may be TC0 or NC1 perhaps we can come up with different clever ways of doing satisfiability and then we get the same level bound that is it. Thank you.