 So, now we will move ahead from where we left. So, a quick recap of what we were doing last time. We are looking at time space, time configuration and I gave an example of this. This is the configuration. First was a time stage, space and time. This is a time multiplex space switch and we are looking at how this will be controlled by a exchange control system. So, typically the way I told that there will be exchange computer which will be controlling. It will be talking to switch block control. Switch block control in turn will actually then control these three different stages. The time part, the space part and the time part. Now, if your switch configuration is going to be different, then this thing will be different actually in this case. Switch block control has to understand all the intricacies of the switch implementation. As far as these messages are concerned, exchange does not bother about it. It specifies only input port and output port and type of operation. I also mentioned about six possible operations which can be executed and since they can be done in unidirectional mode as well as bidirectional in total 12 operation modes. So, that will define the packet structure and the messages which are going to go in this direction are known as type 1 and whatever is going to be sent back are known as type 2 messages. I also told that this is always a master slave configuration. Type 2 message always has to be in response to some message which has been sent to type 1, sent as a type 1 message from exchange to switch block control. And there will always be a sequence number given to a type 1 message. While type 2 message will come, it will have its own sequence number but will always refer to a sequence number of a type 1 message in response to whose that particular packet, the response this type 2 message has been sent. There can be multiple type 2 messages sent back in response to a type 1 message that is possible. So, since I am not talking about anything which is standard, this is highly vendor specific vendors because you need not these components are not built by separate, they cannot be need not be built by separate companies. Telecom operator will not buy these from separate companies and integrate. No, you will buy the whole switch itself. So, as far as this standard which is there by which there will be interface cards here which will be tapping all the information sending it to the exchange control. And similarly, there will be interface cards on this side, which will be pumping the information back and going over a signaling channel. So, these patterns are usually the standards, they are governed by the standard. So, that if you buy exchange from some other company and when the control signaling comes all the way through a signaling channel to this particular exchange thing, it has to be in a standard format and some kind of a common language has to be there. That is where the standardization has to come into picture. Wherever two different vendors equipment have to interoperate, not when it is from a single vendor. So, usually this has never become an standard, I am only giving a sample thing. And then of course, I came up with the type 1 message format which was typically as I think it was a sequence number which was there first one. Message number. Message number here, which is technically message sequence number. Then we had of course, operation code, this looks like a instruction set. Instruction set will usually will never have a sequence number of instruction. Whenever you look into computer organization, they never have message number, but here you are doing, because instructions technically are going on a serial line. This will be a serial line, this can be parallel serial, it does not matter as far as the abstraction is concerned. Abstraction for us is a serial communication. It can be over parallel bus also. So, you will always start with this bit and keep on transmitting till you reach to the end. Framing, deframing always is there. This is not, I am not discussing, but this can be implemented if the distance is quite large. So, where the frame begins and where the frame ends. Usually this can be of variable length, that is important. But I think most of the structure which I am showing is of fixed length deviation, fixed length actually in this case. So, there will be input time slot, there will be output time slot I have explained. This format will depend on the structure here and then of course, ultimately the CRC. So, this was the forward direction, the reverse direction was the response thing which is a variable length thing, this fixed one is variable because there is no other variable length field here. So, this one usually will be its own message number, there will be a information field and this can be variable actually. So, when you send it over data link control, that has to be taken care of by framing. Then there is a reference message number. This is the message number for the type 1 message in whose response this is being generated and then of course, you will have a CRC. Now, let us come to what happens, what is type 3 message. Type 3 messages are not communicated over serial length, that is one important thing. It is sent over parallel lines, is basically that is not like a packet actually. So, this structure typically will consist of, I am just going to draw the packet this frame structure, but this is like each bit will be a separate physical line over which something will be sent and this will be split and sent over to the switches TST. So, usually there will be you have now three components, three stages. So, there has to be component for this, there has to be component for this and there has to be component for this. So, the component for the first time stage will be this one, we call it input time switch. So, I have to specify which time switch number, there can be multiple of them. So, for example, this configuration at 0, 1 and 2. I am not writing the address of the control memory where I am going to write, this is very important. So, address of the control memory where I am going to write will be decided by the number, the control that counter output. So, that will be taken care of in that fashion and that is the reason why I remember I have used this thing as a write cyclic and read a cyclic, here it is write a cyclic and read cyclic. So, all the three memory locations are going to be exactly same, they will be written at the same time. This was the actually reason why it was done, then you will put the control memory content. You will have two more fields, I think this I will explain, one is busy and other one is parity, there is no CRC. So, parity is of whatever you have written here that is the parity, parity over all this content will be done, B is the status. You want to reserve something, you say set this particular value to busy, now call or it is free, only two status will be always maintained. So, when you want to release something, it will be set to free, when you are querying something, this value will come back from whatever is there in the control memory. So, you can use this same bus for writing as well as for reading. Then you will have the second one, because there are now multiple columns which will be there, 1, 2, 3 you have to specify a location, control memory ID and then of course, what is going to go in that. So, there is a control memory, this is known as control memory ID, column number. So, this is one block, this is the middle stage now. So, depending on the stage, this hard wired stuff will actually be built. You will have cm content. So, remember when I have drawn the circuit for a time switch, I have drawn a bus over which what is going to be injected into the control memory is coming. So, that will be coming from these parallel wires or these parallel wires. And then of course, you will have a parity bit, there is nothing like a busy or free slot in this case. Just put the value, it is either connection is going to be on or off. So, control memory content will tell whether in which particular slot, which particular switch point has to be on, only one of the three will be on actually in a column. So, it only gives the memory values. There even if you put a memory value, it may be free or it may be busy occupied both ways. There will be always some control value. So, best is when you are going to release certain channel, do not worry about writing into control memory, just simply set the value to be free. And next time, you can do it. You can actually even make a local data structure and maintain this value or keep on fetching it from the switch. That was for that purpose. And then there is something similar will be there again for the output time switch. We will have ts number. Again, you will have cm content and you will have a busy bit similar format, because again the control memories are here. And what you are going to do is this control memory content tells this for this time switch number in whichever time slot you are putting, writing this. Because every time slot, the address where you are going to write is going to change. That is coming by the counter, which is there in the frame. And of course, this will tell where you are going to write. This will tell from where you are going to read. See that this information has to be inserted in control memory, depending on the switching functionality. This is a control memory content. That is why it is cm control memory content. This tells in that switch what is going to be written in that control, in that particular time slot. Where you are writing this? There is a manual thing in F1 stages. Input stage is 1.9, middle stage. Now, I am coming to that particular thing, that whole diagram, which is there. So, typically the circuit for the type 3, this is type 3 message we call it. But this is never sent over a serial line. So, usually there will be a bus register, which will be driving this particular thing into the bus. This is input time switch address bus. I have written it. I will write it horizontally. I should not write it this way. So, I am drawing two parallel lines. This is a bus actually. Input time switch. And there is a control memory content. Now, for a switch, which will be there, usually you will have some control memory that you will be having. And then there is a time slot counter. Now, I am talking about this is not a speech memory. This is a control memory. In term, it will be now the output will be fed to the speech memory. Same counter will be actually putting up the address there for whatever is a cyclic. So, for example, in case of input stage, it is a cyclic read. You write a cyclic. So, for read operation, this time slot counter will be invoking this and this control memory will be going out. Then you are going to do a cyclic write into the speech memory. This will be directly giving the address. At the same time, you can also write here, because both are happening cyclically. In this case, when you are actually reading cyclically, you are also going to write at the same time, because counter will be feeding the address for cyclic read in this time memory, in the speech for speech memory. That time, there is nothing being used from control memory. That time, you can write into control memory. So, whenever time slot counter value output is being used as a address for speech memory, at the same time, you are going to write into control memory, because when you are reading from control memory, you cannot write at that same time, because this is one single data bus, which is coming out. So, remember the clock cycle will be positive or negative. If the clock cycle is positive and you are using time slot counter value to write into speech memory, the same address will also be used for writing into control memory. If the cyclic write is there, that depends which I have, what is cyclic and what is a cyclic. The basic base depending on that combination, you have to use it. So, for this one, I can just tell. The remaining thing will come for the other one. So, let me draw the speech memory part here. So, this counter is, my notes actually does not have these things, I am drawing it. So, this is the output, which is going to come. Time slot counter value will come. At clock, which will write this, clock, which will put it, it is read write bar. So, because I am looking at the input size, input size time switch, this is going to write in a cyclic manner or cyclic manner. So, it is a right cyclic. So, whenever this 0 is there, this is going to write and I have to take my counter from time slot counter. So, this is 0, this has to be activated, 1, this has to be activated and this is what is going to be fed as an address. The same clock, I am going to use here. So, when I am writing cyclically at the same time, I can also write into control memory. So, this time slot counter will be fed. So, I do not require an addressing, because somebody actually asked me at that time why I am actually using a separate address bus here for writing. So, we are not using that. So, this will remain active. I do not require this selector. That will be the modification. I do not require this selector, because either you are going to read the address or you are going to write and both the addresses which will be used is here. So, in this case, I do not require this actually. So, counter will be always providing the address for read as well as write both operations, because I am reading a cyclic here. Write cyclic and read a cyclic operation. I might have reversed input times which is write cyclic and read a cyclic. At this moment, I have to now insert the clock. Clock has to be inverted actually, which I will be figuring. It is again read write bar or I have to put read bar write. When I put this, I have to be inverting this clock. If you see that at 1 what it is providing that is read of that. So, it is read a cyclic. So, control memory is giving when it is reading on that 1, the selector to speech memory. Yeah. So, when clock is 1. And that write is that that time slot counter should be set straight away put to control memory with the 0. May I am putting time slot counter all the time now? 0, yes. Because I am writing also on the same address, I am writing in the as per the time slot. I am also reading as per the time slot. So, I do not require actually selector here. So, that will be the modification which will come into the circuit. Only thing is that whether you are writing or reading this has to be taken care of. So, when you are reading here from speech memory that time you should also read from here. So, it has to be there has to be known on not getting here in this case. So, means we are reading and writing from same to the same time slot. Same, same time. But it cannot happen simultaneously. Half cycle, half cycle. Cycle you will be doing you can when you are reading from here you are not writing into that. This is a right cycle, slightly can write read cycle. What will say this operation? This is a right cycle. Right cycle. This is a right cycle. Right cycle. Right cycle can read a cycle. Right cycle. Input time switch is let me write down this. I think because what happens the diagram is not there there is a problem. This right cycle can read a cycle and this has to be write a cycle and read cycle. Then you get all the addresses are going to be as per the same actually at any point of time when they will be activated. So, there is a going to be a change in the circuit because of this. Because I am all the time now feeding address only from time slots on. For reading and writing both purposes. Because the clock when it is going to be 1 when it is going to clock is going to be 0 you are writing into this. At that time when clock is 0 here you are also writing into this. But when you are reading from this because it is a cyclic read I am also reading from this control memory. I cannot write into this and this is going to work. So, input data only has to be then there is no selector is required. This data will come from this particular bus. Now what this address bus is going to do? There are multiple time switches those have to be selected. So, when your this data is going to come from here there will be an ending operation depending on what is the switch ID 0 1 2 3. So, it will this address will be mapped on to that particular ID. So, there is going to be some logic here which will convert it to a which will map. It will compare basically this thing with I will call it. There is a data. So, there will be what we call the address of this piece. So, if this address and this address both matches it will become 1 and then data will be written in that place. The important thing is that in one single time slot I cannot write in all 3 control memories simultaneously. It is a 3 control memories. They are all feeding from the same bus. When I am writing the control memory here other 2 control memories I cannot write that is the only problem here. They are not independently addressed. So, in that AND gate the first address is coming from that. This one this is a configured address. For this it will be 0, for this it will be 1, for this it will be 2. There are 2 control lines for this gate. Which one? This one. This gate and yes. That one is coming from this address person. See I can now address 0 1 2 from this bus register. This switch block control. Switch block control can write in any one of the 3 control memories. The 3 control memories here. For each one of these time switches there will be 3 memories. Hence the second input will become. Second is data. Data will be again now similar thing 3 times it will be repeating. For this case the 16 inputs time switches it will be repeating 16 times. So, all data will be coming from here. Everybody will be getting but only one of them will be able to write. You write only in one of them and that will be chosen by this. No, that is what is that AND gate. Is AND gate is having 2 inputs? No, this will have bus. If it is only binary you can only have 2 time switches. If you require multiple it will be bus. This output will be only one single bit but this is a bus. This is a bus. So, it will be repeated in same fashion. And what will happen is you will have similarly 2 more buses. So, this one will contain this is space switch address bus and this is space switch data bus. I am actually kind of doing multiplexing. I am not accessing all memories at the same time. So, if I have to in the same time slot I have to write in all 3 memories. This requires 3 cycles, 3 frames actually. But this is fine control traffic is always going to be less because I am talking about a circuit switching system. So, 3 memory delay will be 3 frames. Yeah, for setting up. If I ask you what is the call setup delay this also should be accounted for. If it needs writing of in 3 memories. Even speech will be delayed by 3 memory. Speech will never be. Speech depends only on the control memory, speech memory. Setting up of a circuit you do not talk actually unless the complete set circuit is set up. So, when you make a dial of something when the whole path is set up after that only you start talking. Once you start talking there is no delay. It is only speech memory which is participating. Control actions are not. This is only when the path is set up or path is released. At that time these will be operating. So, this structure is basically for circuit switching system not for packet switching. Packet switching has a problem actually. I will tell once I come to packet switching. Implementing this kind of centralized control for a switch is a very very complicated thing. And this is actually not desirable in that case. Circuit switching it is fine because you can take care of the delays. Because even if delay is there you talk for 5 minutes delay of 20, 30 seconds does not matter. Packet switching you send a packet. It takes few microseconds to transmit a packet. You cannot set up a circuit and take 2, 3 seconds for transmitting only for few microseconds. That is highly inefficient. Then you come to those special structures which will do self routing. So, this class network usually will not work out in this scenario. Because in this case you require centralized control. That has been the problem. That is why these configurations are not used. Even if the blocking is there we go for bunnyun kind of configuration. The third one is again very similar to this. It will have a output time switch address bus. So, I am addressing each switch not the control memory address. Control memory address is going to come from time slot. So, somebody was asking so this is actually the way it happens. I do not generate a address from switch block control. Of the control memory address we never generate. And this is the output time switch data bus. And this whole thing together is what is known as type 3 message. Data bus that is control memory content. Yeah, right. It is a control memory content. So, now there will be no... CM content bus. So, now there will be no delay cell. What we spoke just now. Because if it is going parallely then now there will be no delay cell. But only you can write only in one control memory. Usually for setting up a circuit you need not write in all the 3 control memories. You write in one control memory here, one control memory here and one control memory here. All this can be done in one single time slot. But if you have to do a lot of rearrangements and everything then it makes... You have to then compute the timing. If you want to make it for example rearrangement on blocking switch. Mostly you will never be implementing a system on blocking. It will mostly rearrangement on blocking or a blocking configuration. Then of course there are issues. But there is something more to this circuit. This is not the complete thing. So, I am going to change. There is a parity in this. Parity and... Those also goes on the data bus only. But in the address bus itself there is a control memory as per the format you have given there. Address bus. No, this is what is the address bus. This is what goes on the data bus. This is what goes on the data bus. Similarly here this is what goes on the address bus. This is what goes on the data bus. Address bus and... This is the address bus and this is what goes on the data bus. And parity is always used to check, verify whether things are correct. If parity break happens some wire might have broken on the bus. So, that guy is always getting 0 or 1. Depending on whether it is a basically pull up or pull down kind of configuration. If it is connected with a register to the higher voltage it will always become default 1. By pull down you will make it to 0. If it is grounded to a register it will be pull down kind of configuration. If you leave it floating it is pulled down to 0 or pulled up to 1. Now, there is something more here in the box. So, I am going to just erase this text I think you have already noted down and draw the remaining component of the box. Usually there will be a status register which I call a record of whatever is happening everywhere. So, all busy and parity all those bits will keep on coming from this side from all of them and they will be pumped here. Because that is the only thing which you require from the control memories. So, those can come through again by putting up the wires, extra bus lines and this will maintain the status register we maintain here. So, there will be a separate switch block control processor. Usually that processor will scan through the status register or this can be maintained as a data structure in the software. And this value will be taken whenever a message will come from here. There is a path selection logic and the path selection logic will decide what has to be written into this bus register or what will be the type 3 message. And this has to keep on changing at every 125 microsecond. Every slot actually it will change because slot will decide where you are going to write it. So, if you want that in this particular control memories a specific location you want to write in that slot only this bus register should have that value. This will be enabled. So, this also need to have a clock synchronization coming here. So, clock will also come down to this box switch block control because you will apply only in that particular slot. So, every slot this can change. So, in every frame you can actually write 125 sorry if it is a even frame you can write 32 variations actually 30 variations technically. And those will be kept in the bus register it will keep on flipping every time slot. So, it is also kind of sending frame it has to be in the frame sync. It is not kind of you just apply something and remains there forever no it is changing every time slot because you are not sending the control memory address. So, that is the penalty which you pay because you are not sending control memory from switch block control. If you can actually bear the cost additional cost you can choose to actually even have time slot address plus actually control memory address also in the bus. That will increase only number of bits. So, in case of that 30 channel system you require 5 more bus wires here and 5 more bus wires here that is it. Then you will have a selector and all that thing here and this CS counter will not be used for writing into this thing. Then you will do a selection only for read purpose this will be used for write purpose you will use a address generated from here. Advantage is that you just can decide here and put on the bus. You need not fetch this clock which has to be in synchronism in all the three time switches remember. All three time switches I require frame synchronization. All three frames have to start at same time they have to end at same time. So, that requirement is gone but by putting additional wires. So, even though it looks simple and trivial it is not actually. So, all timing has to be synchronized or all three usually it is time synchronized. Otherwise if these frames are not synchronized you cannot do switching here. A synchronous operation actually is not possible in this case. So, this is switch block control but processor I have not shown. These are the block of codes or a hard wired logic which will be always used. So, whatever is the type 1 message will come to pass selection logic outcome will be sent by. Actually it is a processor software which will do it. OS of it. So, these are like separate code OS will maintain the queues it will just pass the message between the queues and execute the processing logic for each queue of them for the messages. So, OS part I am not discussing here I am just leaving it to your imagination. So, this is your switch block control. Now, the pass selection logic what can be used here? And I think I can whatever strategy you tell most likely it is going to work only it may not be efficient. What is the meaning of having a pass selection logic? Remember type 1 message only tells this is the input port this is the outgoing port set up a connection. It does not tell how when it has to put in how you have to decide what is going to be the common slot between T, S and P. And this will decide what is the control memory address which have to be put. Incoming and outgoing sequence numbers these physical ports will anyway fix switch which control memory which control memory here and which control memory 3 control memories are identified by that port number. But the location inside have to be searched one very simple strategy can be let me start from 0. If the 0 time slot being used in all the 3 control memories or not. I am trying to find out something which is common free in all the 3. If 0 is free in all the 3 control memories coming from this status register. If 0 is free fine I can use that based on that I will decide on my type 3 message and apply. 0 is not free choose 1. 1 is not free 2 3 4 5 so on till you find something which is free. If you cannot find something is free you say I cannot set up the connection it is all busy. This is known as sequential search but starting always from the same starting point. What is the harm in this kind of a strategy if you start using this. Same 0 will be used over and over again. Fine so what happens is most of the calls will now be compacted towards 0 1 2 and 3. Higher side will not be used. As a result whenever you are trying to make call whatever is the average number of calls which are there at any point of time. You have to search at least those many number of times you are instantly wasting your computation power. I can probably do something is still better. What could be that is still better? Random do a coin toss do a random number generation based on that decide. There may be chances of collision and if there is a collision again do a random coin toss till you find something which is vacant. But you cannot be sure that all slots are busy you will never be able to tell that actually that is one problem. So what you will do is how to because you are not scanning all possibilities. Then how when you will stop? Will you keep on trying all the infinite time till it gets you randomly find and call it gets through. No. So what should be the strategy then? No that is a search strategy I am still doing random. So you will do random search but only certain number of times. You would say try for 10 number of times does not happen you say why it cannot be done. Probably loading is very high. So that comes from your probability estimates actually from there you can figure that thing out. Sir instead of searching we can have a list of free slots whenever a slot is free. Only all slots has to be free in all three. Yes sir when all the three are free. But which three pair that is a problem this three pair is not three couple is not fixed that depends on the actual physical input and output port. So the all possible combinations you are looking then. So it will be three into three into three. The 27 sets which you have to manage at any point in time this is going to be cumbersome actually it is never done because of this. And when the switch size I am only talking about three port when you buy how many physical ports are there think of that. So it is going to it is not going to work actually. Second possibility is that sequential search which I had you do a sequential search this controller will actually remember what was the last where I finished my last search. So I did 0 1 2 3 4 4 I finished 4 was perfect fine. And then I remember the 4 next time I call the question I start not from 0 but from 4. So my initial value of the search will keep on changing actually where I last finished. And I keep on doing it this way and I will do a round problem. So one of the good things I will try to utilize all cross points all memory locations equally. And if the gaps get come they will also get filled up over the time. So this is one good possibility which can be sequential search but the starting point is not always 0 it is where we left last time. And if you do the complete search and you come back to the same value which is busy you simply say call cannot be made. So this can be done within a finite duration it is not infinite the way it happens in random. So random you decide certain numbers for which you will try. So you at least know so maybe you can say you try at control stand and then you can discard that is also possible. Let the guy try it again. And your call will be actually dispersed across all the possibilities uniformly. And what happens is you take these three combinations call is blocking but you take these three combinations same slot might work out. So that is another problem. How much efficient is this? How much efficient is this? I do not know you have to estimate it. Instead of starting from last search why we will start a random point and then start from That is also good possibility. Yes. Because directions can be random that is a good thing. But even if this switch is rearrangeably non-blocking so even if it gets blocked Yeah. If it is rearrangeably non-blocking then you can do the rearrangement. Then you have to use all that rearrangement algorithm. But if I am not making a rearrangement it is a blocking switch or anything and I can do random thing. Remember either what we have done is when you are looking at a blocking probability using Carnot's approach I have used a random search thing there. Randomly things are pretty equally likely all possible combinations. Now can you correlate what I taught there and what I am discussing today? So that algorithm that formula is now executed by the processor setting in the switch block control. So that was not something fictitious that was the reality actually. So the moment you change the strategy your computation or probability of blocking calculation strategy will also change. That was also three stage switch this is also three stage switch. I can now increase or decrease my number of slots here. If the number of slots here and here it is rearrangeably non-blocking but it is still blocking switch. It is not strictly non-blocking. So blocking probability you can estimate and blocking is not happening because of this switch in those conditions. So that is a correlation between the two. So I think that is where we will end our circuit switching discussions. And I think of your own if you want to pursue circuit switching you have to do your own study. There I think lot of papers which are there which have come out on various different kind of switches talking about their designs. But we are not going to use any more circuit switching case scenario except for optical circuit switches which are still a viable thing. But electronic circuit switching I think this is now a thing of past almost. But not in optical domain. Optical domain packet switching is still very complicated and difficult to implement. Optical circuit switches are going to stay. The reason for that is you can build up reconfigurable topologies there. So underlying physical for example this router is connected to the other router. I can tomorrow choose and make somebody else as my neighboring router. So the topology is nothing but a graph which represents the connection between nodes. That itself can be modified by optical circuit switch network. So but that is anyways not part of this course. So we will discuss that in optical network course. So whenever I am going to please that. So now what we will do next time. So I think till this point we will have everything coming to place. So next lecture will not be part of the medicine. So that will be on packet switching systems. So how you will implement packets? I am just introducing here because only that much time is left. Packet switch will still be a box. We all know that. How to implement it is the question now. What we want in the packet switching system? What is coming at the input? Let us start from there. There will be some inputs you all agree and there will be some outputs. So like your PC is being connected into this switch. So what comes in? It is not bytes. It is a frame. It is a packet which is coming in. And what typically a packet will contain? A special control information has to be inserted. Each packet is an independent unit. It has to be having a header. And then of course the information which you want to transfer. Now each packet which will be switched inside this is not it is not like that somebody is doing a signaling and it is setting up a path and then whatever bytes you will pump will always take that path which is what was happening in telephone. Here when this comes this header will decide on which outgoing port it will go. On which outgoing port it will go. This header will decide. So there is no signaling. That is one very good thing. Do not require any signaling. Your signaling information is going with every chunk of information. This also means how many packets are coming per unit time per unit second on each line. Those many chunks of control information will be coming and that has to be processed by this processor. Circuit switching. How many control information has to be processed? Number of calls which are set up per unit time. Once you set up a call it is through. You are talking for two hours. There is no control information being processed. But here I am not sending a whole packet which is of two hour duration. It will be very short duration. This actually puts a lot of load on the switch. There is no doubt I think. This processor actually takes a lot of load because of this because for every packet which is coming in it has to get the header out. It has to analyze that and based on that decide where the switch will go, where this packet will go on which outgoing port. It has to do something in this box so that this packet can come here. How this can be done? Now I am asking any idea how this will be done. You have already done circuit switching. Lot of it. You understand the cross bar. You understand clause everything. Can I do something with cross bar? Let us start with that question. Can I introduce more complicated stuff? Can I do something with a cross bar? Is a 4 by 4 switch for example? I use a 4 by 4 cross bar. Can I use that thing for switching the packets? Can be done. Maintaining the mapping. And most important thing. And I am going to take a simplifying assumption that all these packets are synchronized. So packets on this port and packets on this port are all of equivalent. They always start at the same time. They always finish at the same time. Next set of 4 packets will come. Next set of 4 packets will come. That is how they are coming in. Actually this assumption is very important because if you are operating in this mode this switch will be having maximum efficiency. So operation becomes very easy. Otherwise implementing a switch is complicated. So most of the designs are basically based on this kind of structure. I think this is one of the reasons why asynchronous transfer mode ATM actually came into being and that was having exactly fixed cell length. 53 bytes. You build up the cross bar depending on whatever are the packets which has to go. So I have to get all these headers. So there is an interface board and this thing I have to do the processor at the central command. Based on that I will do all setups of the circuit. Circuits will be set up for exactly one slot duration now. Cross points. So once the cross points have been set up so there has to be some delay. So that this setup happens exactly at one boundary because when the packet is received first only in time. You receive these packets. Here I am showing this as a time excess. You are receiving even others. You will receive the complete header by this time. It will take some time for you to process all the headers which you have received at all the four ports. You will be able to decide by this time actually now. It will take some more time and after this you will be set up the cross point. So you have to insert this much delay and at each input. And then by this time cross point is set up it will go out again in synchronous fashion to the outside. The next packet will come. Again all headers will be processed. By that time this packet goes out the same delay will be required by this to process and I will be able to send the next packet. Packet switching can function. My only condition is that I should be able to process all the headers in one slot and that actually means number of ports which can be there in a switch is limited by what? Processor capacity. So you cannot keep on increasing your number of ports unendingly. That is not possible. And this becomes still more complex because you have very high bit rate lines now. You put an optical interface 10 GBPS and you can say now I can have very high throughput. You put in lot of packets but you have this guy the processor will not be able to process it. You need to reduce your number of ports. You need to reduce your number of ports. So throughput is actually usually limited by processor capacity not by ports. So what I will do is I think this is a good idea. What we will do is we have to improve on this. There is a problem here what? Can anybody guess? Contention. Output contention. Output contention there are can be more than two packets or more than one packet trying to go to one single output. What you will do? Only one can be done. One packet will go other one has to be dropped. There is no dropping mechanism here in this case. There is no dropping mechanism. Basically what you will do is only certain cross points will be activated. This input cannot go for example. So that no cross point will be activated in that case. Multicasting is pretty easy. You set up all the cross points from one you can go to all four. Remaining you do not set up and that packet is lost. So contention cannot be handled in this case. So this is blocking in that sense actually. It can be blocking. So you have to stagger. Stagger in time. You have to stagger it in time. We have to have a certain queuing strategy and some strategy by which it has to be done. So we will try to analyze what I can do is I can put buffers here. So no packet is lost. I have a memory. So buffer is first in first out kind of queue. So if I put at the input, what is the performance? If I put at the output, what is the performance? So that is I think is the first fundamental question which we will investigate. So this is actually from a paper. So that paper I will upload on the Brass Party. So you can download that and go through that also. That gives in much more detail the whole thing.