 Hello everyone so welcome to the lap 3 of design compiler in the last session we saw how to set the design constraint and compiler design how to we saw how to create a clock so I have just loaded all the commands that I set here so you can type a command called history so this is what I did I just to do the steps we set the search path we set the link library target library define the design layer this is we read in the all the RTL files we elaborate now at this point you should set the lock the warning after elaboration we should set the input support what all blocks are in for what all how the case and case of what it is important whether it is full case or normal case when we start setting the of the environment condition because the top reading condition I will discuss about this command later so set operating conditions I forgot to set viral we could do that let us assume whatever default by load it is let us take that it will not be a problem we set the input transmission on input ports we set the load I also discuss how to estimate the value of input transmission on load by looking at the matter then we go on and set the design constraint we set the clock we set the uncertainty the clock transmission then we set the input delay and the output delay so here in this case the max delay and the input delay is set for both mass and interfaces we will see the usefulness of this when we come to this static time analysis in a minute time so this is the you can also define variables in DC it is a technical interface so everything that works in typical works here so you could define the variables like this input port we define the variable input port remove from collection all inputs then we remove the clock so we define the input delay and output delay using these variables and now I go ahead and compile so last session we saw that compile by default we will ungroup some blocks it will ungroup some hierarchy and to start with we do not want that obviously it results into a known area but in many cases we do not want that so how do we do that I just search for a variable that affected so what we would do is we would run in a simple format by using no auto-ungroup no boundary optimization and no sequence now so in the next few lecture sessions we will see in detail what each of these means and how does each of these effects so meanwhile let us remember that when you want to do a first session without scan without any sophisticated optimization technique this is the command if you do compile it minus no sequence and output inversion minus no auto-ungroup and minus no boundary optimization this is the you could use no design rule and only design rule to control or incremental to do multi-passing multi-passing you want to do synthesis in two or three I will see but for one part synthesis this is the basic command so we will do that and so it will start running synthesis now after the synthesis is done what we will do is we will learn about the report commands that means now synthesis is done you want to check for all sort of issues you want to verify that then at least you have generated the area and the timing results are fine whether they are in line with your goals or not what is some of the design rules is validated how do you and we will see what all reporting commands we could use what are reporting commands we could provide that for reporting and analyzing issues and so it is going through synthesis it goes through different sorts of phases sequence optimization, delay optimization design rule fixing then it will go into the area recovery phase so it is a good thing that you should at least once look at this compile log to see that sometimes what happens for few blocks it will take a long time in one of these steps delay optimization or area recovery then you know that something maybe is not right with your constraints it is taking too much time few of the blocks I work on take more than a day in some of the cases so I usually try and make sure that my constraints are all right and try to take in the runtime because we do not want big runtime for block because each error then each resolution of another will mean that much time added to the block so it is difficult to get that block out in time for the for the back end so it is very good practice to review this compile log to see how much time it is taking once per block when when you start synthesizing it now I will write out the netlist format very long output I will write the chip copy or overwrite the file I want to write the complete high so let us see let us look at this so now let us look at the module so we see that now we have all the modules here in group right at the end you will have the top level module chip top and you notice that since the article was over the structure there was very there were very few there was not a lot of logic so the only logic that is in line is the core invertebrate and all these all these modules are instantiated here you could go to one module and see this is the module it only has a couple of different instances for example the module about this this this module is a power controller has a lot of financial logic these are the CSS are nothing but they are blocks so all the blocks here would be non-scan blocks they will not have a TIPIN they will not have a DIPIN you will also see what what happens when we do a scan option we will do that later this is a netlist now let us go back to design compiler and learn about the various reporting commands that are provided so first I will discuss the simple commands for report design so all the you could know about all the report commands by doing the report stack for report and SQL stack so these are all the report commands that are available to you many of these commands are restricted for specific use cases there are various features of design compiler like design compiler, graphical, design compiler, some of the commands will work only there so we look at one of the more famous commands we already looked at you we have looked at report list we looked at report clock so let us ok the first thing let us see let us get a design summary by doing the report design let us see what the options are so report design just has no speed and a physical option physical is not applicable for us it is applicable for DC local graphical so time information also provided but we will not be looking into that the no state is a is it option that is common to a lot of report commands and it means that whenever the line overflows it will not split the line so whenever you are viewing it on screen then it is alright not to give this option but whenever you are writing into a report file I would recommend giving the one those three options so right now I am viewing it on a screen so I will just do report design so now it gives me a summary of a moment it gives me a summary of library view it gives me what is the link library it gives me if I have provided any restriction from the type of lift off and back to view I have it so there is one specified it tells me what is the operating condition here it tells me what is the by load model now in this case I did not apply a by load model for this session last session I discussed about the command that we can use to provide a by load model but this particular version of standard cell library contains the automatic by load collection so it is selected automatically from the profile area the default is the default is a top so it will apply only it will take only the popular by load model for all the high critical designs okay so it is it is not using and it gives us it is strange why it is not giving input delay and output delay let me just take report command so report port can be used to check what all input in a data so it makes there will be problem with the report design sometimes there are bugs between the two versions so here it tells me that there are in fact input delay specified so what about the output delay yeah output delay is also specified but strange that report design does not tell us that it tells us that input delay is an output delay and output delay is an output delay it says that there are fin input delays and fin output delays but what is specified as port yes we have specified input delays and output delays are usually specified at post there are some cases where we would might want to provide input delay and output delay for some internal thing but that is not recommended it is used for very very special case which is outside the scope of this code do not worry about it so yeah report report design will tell you what all it just gives you a summary of all the design parameters so I would recommend to use the specific cases for example if you to report the commands for example you could do a report lipo library you could use a report viral model to check what viral model is used so this is the report viral which is much more it provides much more detail than report design so looking at the report design I would recommend to use the more specific reporting commands for example you could use report for some of the reports to check that whether that the input and output delays you have applied are in fact here it has been written by DC again we saw this report block we can verify what block is specified here what is the frequency of the block what is the waveform DC is using then this is very interesting the model called report QR which reports the summary of the quality of the words let us see that so let us see the summary first so significant digits is will be used for timing number timing and validation number where you could say that I guess by default it is 2 or 3 I guess I think it is 2 the period is being reported as 2.00 so the byte upon the significant digit is 2 I guess let us look at the summary first so now it tells us that it gives us the timing summary so it tells us that the worst negative slack is 2.99 nanoseconds that means the worst critical the worst timing path worst data path is validating by 2.99 nanoseconds total negative slack is 2.7.56 number of validating paths are 97 we will see we will see what it means in much more detail and in time flight and time so TNS that is the total negative so WNS is the worst negative slack TNS is the total negative slack which is the summation of the negative slack of all the so all the 97 validating points okay I think I have not explained what is slack so we I will explain that it will make more sense it tells us the area it tells us that there are no whole constraints which is fine it tells us that there are no nets which have the articulation let us look at it will provide any more information so it gives us the quality of results and statistics for the current design you can specify the significance with it Mario is more applicable for us okay so we did a summary now let us look at the detail report detail report is much more bigger so now it tells us that the clock n is clock yeah so it tells us this is the clock n is clock so we know that there is only one clock so it tells now per clock what is the statistics so let us tell you have multiple clock there are multiple entries here it tells us that the maximum levels of logic at 12 levels of logic means that between 2 registers how many combination elements are there maximum there are 12 critical path length is 3.69 that means the path delay we look at we look at the one of the timing reports and see what it means by the which then this things will become clear so it tells us the summary of the timing it tells us what is the cell count so hierarchical cell count is 44 that means this is the total number of hierarchical cell right it tells us what is the lead cell count now lead cell count is the total number of cells in the morning so lead cell means a cell which is not hierarchical so any standard cell any memory is a hierarchical cell because there is no other cell inside it as far as design comparison so for example an inverter is a lead cell because inverter is the lowest level of hierarchy that DCP similarly memory is a lead cell because why because we read the dotlet for the memory and DC does not see anything inside that it only knows the timing information and the area information for the cell so any cell like standard cell or a memory is a hierarchy is a lead cell it tells us what is the number of buffer than inverter so number of buffer than inverter it gives us the summary of area it tells us what is the combination area non combination area is sum of all the sequential and memory cell that area is estimated from by load model so it tells us what is the cell area so cell area is sum of combination and non combination design area is sum of cell area and that area it tells us that their total number of nets are this they are no nets which comes from the solution it tells us which machine did we did we done it tells us what is the resource sharing their some numbers of logic optimization and none can optimize they can so these are the time it takes for resource sharing logic optimization and not in optional different overall compile time is 60 seconds out of which these very seconds are used for resource So, report QR it gives the summary of the all the violations and the area right now let us look at again look at the specific report let us look at report area. Now report area again it tells so there are many kinds of reporting commands and some information is common to let us for example report area and report QR both tell us what is the area report area is a much more specific command. So, it tells what are the libraries used number of ports, number of nets, number of cells, number of references, number of references means number of instances, number of nets then number of cells is the total number of cells in the top limit not the we will see how this number is welcome, number of ports is total amount of input and output ports. So, you could let us say I want to so I want to know how many inputs are in this design to know the number to know the total number of inputs we say all inputs there is a command to nice command called size of collection. So, I do a size of collection this gives me the number of elements in a collection now since all inputs gives me a number of number of input I can tell I can use size of collection to know the number of inputs here. So, number size of collection all inputs tells me they are 34 inputs I can do a size of collection and there should be a all outputs 67 outputs so we sum both of them we will have the number of ports they have 111 right. So, there is there so that we can see how many commands like this are so there are these are come the commands to get the collection so all inputs all outputs all registers you can also see how many registers are there in this design you could do this there are 723 sequence registers here registers means they are all pictops in the design and so on. So, but these numbers here number of course, number of later number of cells they refer to the current design with the top level design now let us I want to point out a few things in the netlet let us open the netlet again. So, let us go to the top level design which is the last entry this the number of cells here is this is one cell instruction decoder 2 3 4 5 then we go down and see 6 7 8 9 10 11 and 12 that is reported by the report. So, if you want to know the total number of cell across the complete design that means you are asking for the information of hierarchical cell. So, the one reported by design compiler report area command is simply the top level it refers to the top level design or your current design. So, you could go inside let us say you want to analyze a design which is some hierarchies down you can change the current design to that in another report area we will we will see my example let us see let us see what design we want to let us say I want to know what is the instruction decoder area separate area right I want to analyze now I want to go inside and analyze how much area does each of my module take. So, I can say a current design I can change it to instruction decoder and now I do a report area. Now it tells me that for this particular design it uses only the standard cells it does not use another because there is no memory inside it tells me the number of ports net cells number of references it tells you what is the combination area not. So, you could go to any part of your design any part of the hierarchy and do a report area on that. So, lot of commands most of the commands in DC work on the current design. Now I want to reset the current design to chip top. So, this this was all about report area. So, we saw report area report you are now let us look at the. So, the the the commands are used the most which are most effective report area then there is a command called report constraint let us see the very interesting thing it is again give the summary of all the report constraints as the names are there tells you it has a lot of options it tells you what all constraints are there in your design and if some of them get violated how many are met it gives all kinds of information. So, what I do I just do a report constraints without anything. So, we see that all the options here are they they lend a specificity to this report constraint. So, you want a very specific information let us say I want a summary of how many setup violations are there in my design. So, I do a report constraint minus all volators all volators will give just the volation I do a setup is the maximum constraint strange okay. Let me see just all volators it says that this design has no volator constraints and I have doubt about it I do a report okay. Let me check this design something has looks like somehow the okay looks like when I change the current design the constraints over written. So, what we will do is we will compile design again and we will apply the class and input out to the measurement usually it should not happen, but looks like there is some bubble disorder I just okay let us compile the final one. So, I can do a just like this I can search for the last command now let us look at report constraints minus all volators. So, somehow the constraints got raised from the design I am not sure why may be I play with the current design. So, that is why now what happens here is now report constraints minus all volators is very useful command which gives you a summary of all the volations in the design. So, now it tells me here that there are win delay hold volations win delay and hold is same we will see why hold is called a win delay the clock rope means that it is working on this constant clock. So, all these end points there is the volation of this much nature right now let us see now this tells us just the pin where there is a volation we will see what it means by part delay and required and actual part delay by looking at the report timing command and the flag. So, now let us see the most reverse amount of all kind of the report timing command. So, what are report timing command has lot of options. So, then I will after explaining the report timing report I will go back to some of these commands. So, it has a probably the most extensive command there is in DC or time time report timing CC it has lot of option as the name suggests report timing is used to see report a timing on a particular path right. I just do a plain report timing and see what will happen. Now a plain report timing will give me it gives me a report timing part type pull means it will report on the cell in the path delay max that means it is a set up so, there are two kinds of reports max report and a min report max corresponds to a set up report then corresponds to a hold report. Number of parts so, delay max means it is a set up kind of report minus max parts one. So, these are default options that shows max parts means it gives me only one part minus. So, you could want more than one parts more than let us say you want to report the five words part you can do that it tells me that design is the instruction decoder. So, there is a problem with the current design that is why the things do not happen and have to be again so, the current design is instruction decoder which is not we what we want we want the chip top. So, let us sorry about that let me change the current design to chip top again or I have to clear the memory. So, if this is a variable that contains that controls whether so, as soon as I change the design to instruction decoder to show you the area report what design compiler did was it remove the other designs from the memory that will not be used that is why we were having all these problems. So, I will I will once more do stuff or once more read in the design it will take hardly a minute and I will set the things again. So, that is why it is useful to have a report like this have a script like this if you can run instantaneously I will do a compile again. So, I did a chip top level I was expecting to see some set up volitions I remember from the last session, but I did not see any set up volitions if you remember in the report constraints I only saw whole volitions. So, as now I have hopefully I will see some set up volitions. So, what I have missed applying is the load and the transition numbers we will do that we will see. So, it is a blessing for us. So, we will see the usage of incremental compile. So, now I am synthesizing again with the plot in place with input delay and output delay and I have missed applying the load and the transition. So, input condition let us see how we can solve for that that. So, now there is hardly any design rule fixing it goes down very quickly. So, this is now let us look at the report time or report let us look at report constraints again. Now you see now it also tells us what is the maximum set up volitions. It tells us that there is an end point on which there is some set up volitions right. So, it gives you a report complete report right. So, what you could do is now you could do specific, you could say show me only the set up volitions. So, it shows only the natural evolution, specific report. Now, let us do a report time. So, now the design here is chip top which is good operating condition, library, download model. Now, this is the start point. It tells me that start point is a rising S progressive clock, clock by clock. End point is an output port. Part group is clock. The part group is the clock name of the clock that captures the end point. Now, why do we say that clock captures the end point? Because we have specified the output delay on the output port with respect to clock. So, this type of path is called a register, register to output path. Part time path is a set up report. Do not worry about this. It tells us that the download model this is the important part. Now please note that a set up path is a path between is a master type of path and the start it starts at one clock is the launch clock is and the data is captured at the other clock. So, this is the launch part this is the launch part. So, now let me also do a report clock. So, the clock wave form is 0 1 clock rises at 0 falls at 1 clock rises at 0 clock network delay clock is ideal there is no. So, the there are no delay specified on the we have not defined any network delay. So, you could define set clock latency. So, if you specify a positive value to come here this is 0 for a while. Now, this is it goes to the memory C pin it goes to memory output pin this part INCR part is the delay that is consumed by a cell. So, here memory consumes this delay the path delay is nothing, but the cumulative effect. So, these are this is the list of cells that are in the power it starts from a memory goes through some combination of it goes to the output port. Each of these cells. So, here only output is listed each of these cells consumes this cell consumes a 10 ps delay this consumes a 30 ps delay it is a memory. This consumes 30 ps again 40 ps, 60 ps, 70 ps and here there is a cumulative path. So, the data arrival time at the output when the launch clock is at 0 is 3.64. Now, the capture clock comes at 2 the complete total period of the clock is 2 2 nanoseconds the launch edge comes at 0 for set of the capture edge comes at 2. We have specified some clock and sets will be which means that the capture edge can come a little bit earlier since it is 0.3 it gets subtracted. We have specified an output external delay that means the data should come at least 1 nanosecond before the capture edge. Capture edge is at 2 adjusted by the uncertainty it is 1.7 data should come at least 1 nanosecond before capture edge. So, data should arrive by 1.7, but data is arriving at 3.64 there is a problem. So, the data required time is the time at which the data should be stable data arrival time is the actual data that arrives. If the data arrival time is less than the data required time we say that the time will be valid. So, slack is the margin we have in this case the margin is negative performance. So, it is validated. Now, this is the register to an output port path. If I say now let us look at in various options that are available to us. So, now after this you should be clear about what is meant by a data required time what is meant by data arrival time. Now, let us look at report timing minus 10. There are so many options now you could go very specific. If you want the timing between two registers you could do that by saying the report timing minus from and minus 2. You could go even more specific if you want right transition and false transition or you want to record a timing to a particular path. If you want the timing if you want to increase the number of paths for example, what I would do here now now here it reported only one path. So, what I would do is I will ask it to tell me I will ask it to tell me what are the worst let us say 5 paths. This is the worst path the slack is minus 2.94. Now, the second path start start point and so, now it gives me 5 worst paths. Now, we see that now see report timing is for detail now on the other hand report constraint was saw a more summary kind of a thing. So, I give a report. So, what I will do is what is the good practice what you could do? You first you do a report constraint minus all validers do a minus no state and redirect it to a a valider report. I will do a valider. Now, you go back you open this report and see what are volitions are there. Now, I see here that the end points are all output points. I would worry more about register and register volitions than the volitions can input and output I tell you one later. Now, let us focus on the register to register path if there is any volition. Now, we see here that there is some pin here that wallets and it is not a it is not a pole. However, it might have a volition starting from input pole this is just the end point. The leftmost column is the end point. So, and do not worry about the pole volition anymore. Let me see if all these pin the reset things. So, they must be similar kind of path. Let us see what what is this volition? Now, I want a specific report. So, I go back to report time and I say report time minus 2 and I check out this one. So, now, see the start point is a register and the end point is also registered. So, this is a register to register path. It tells us what is the valid model used for different designs in the automatic area based value model. Clock rise is a launch part. Launch for a register to register path will happen at the clock edge if you go back and see the lecture side. It starts at the clock edge it goes from clock to tube clock it goes to all these combination logic. So, there is a bit bit combination logic. It goes to be multiplied register pin there is some clock register pin. Now, here so, then there is a the launch clock is a 2 sorry the capture clock is a 2 I will just say the register for uncertainty. Now, when we saw the register to output path we subtracted the output delay. In this case, the output delay is replaced by the larvae set of time. Lavae set of time is such that the data should come this much time earlier than the capture edge. It is a set of time so, it is subtracted again. So, data required time is 1.57 data arrival time is 2.92 slack again it is validated. Now, what does this tell us at the first glance this tells us that R design is not suitable to go at 500 megahertz why because for a violation of for a clock period of 2 nanoseconds R design violates by this much amount. So, I will do now I will do some calculation my period was 2.21 the violation is 1.36 for register to register path. So, if my period was 3.36 nanoseconds then this might have met. So, this is a straight forward calculation. Now, I calculate the frequency at 297 megahertz without even going to for the compilation I can say that not available. This is how we estimate the performance of a design and now we know that this design will not work at 500 megahertz. Now, they can be multiple because first reason could be that you are aiming for a much higher frequency, but the design is not good. Second indication could be that the design is good you are confident on a design, but it is not supported by a statistical algorithm. Now, in this case for example, we synthesize a design in 69 nanometer, that is 5 ohm was I am not able to know the design. So, what you could do is that improve the design or decide whether you want to go to a lower technology because if you go from 69 nanometer to 49 nanometer your standard price will become faster. So, this performance is fully limited by both the design. Now, here one thing I see that there are so many combination elements in this in this critical path. So, this is the critical path critical path means this will be violation worst case violation on the risk to make the path. I see there are so many levels of logic here. I see there are like about maybe 20 odd and when there are 20 levels of logic 500 megahertz is a bit very high frequency right to aim for. Now, somebody might ask that let us open the violation report again. Now, somebody might ask that there is more violation on the outer force. So, why are you worried about this? Now, let us see. So, what I will do is I will just this is the way you could report the worst path ending at the outer force. Now, it is the same report as before. Now, I see that there is one more factor here which is output at some degree. In the register to register case, it goes to library set of time. Now, we library set of time is something that is true you cannot play with it, but output external delay is something we can play with. Now, I am assigning 1 nanosecond to the external world. My period is 2 nanosecond. I am assigning 50 percent of the time to the external world. This is one problem. I could play with this. If I know that the other the part of the that is capturing this this output code does not need 1 nanosecond. So, I can take some time away from it. I can reduce my output today. So, that will reduce the evolution. Second problem I see is that the path starts at memory. Memory itself is taking 2.9 nanosecond. So, I can never go faster than this. So, the memory is slow right. Third thing is that if the memory is slow then I should not have a path from the memory to output code. I should have a clock. I should have some kind of pipelining here. So, this is there is one guideline that is walleted here which is that I should register my input and output. If this output was registered that means if and if this when so usually for slower memory you should have a pipeline of that means there should be a clock right after this. So, what I would recommend you is to you is that you go back and understand the design of it and see if you can improve it. First thing I see is that these drivers are this is an X0 driver which is a very very slow driver. So, maybe I could up size it. How I can up size it? So, why is DC using a low driver here? Why is it not up sizing? DC knows that it has a big violation and we did not have any design group and we did not apply any descriptive design group constraint apart from what is in the library. So, it does did not optimize this path way. So, it happens lot of times when there are violation when there is a flag between different groups and DC will will optimize one group of path at the cost of other. Now, going back to the constraints I said that I cover to apply the I cover to apply the input function of output load. Now, what do I do? I can do it again and apply a set input condition. Let me apply a 0.5 at the form collection all inputs I apply the load. Now, do I need to do a pull-tump pile again? No. Now, I could do is I did the I did this pump pile. Now, I will just add an implementation. So, I updated a constraint I updated the design group constraint it is not a very major thing. So, I can choose to do an implementer which will be comparatively faster than a pull-tump. So, now it will do design group fixing and it will spend a bit more time on it. So, there are some violations. So, in case you did an implementer since it does not find that it is not improving a lot I will recommend start from start again because starting from start so see there are there are design group violations there are there no design group possible. So, design group is not there. Now, let us see the timing again. So, now you notice that the inverter that drives the output is now upsized. So, this is now an X state inverter why an X state inverter because we specified a load and increase load. Now, forget about the timing problems in the design I will just show you the power of report timing. So, what all we could do now I will I will speak some some typical scenarios I will talk about some typical scenarios and how to report timing on that. I want to see the worst case timing starting from an input port report timing minus from all inputs. Now, this command will report timing starting from all inputs and going anywhere either to a register or to an output port, but it will show only the worst case path. This is the worst case path it starts at an input that we specified it goes to an endpoint which is a register. So, it is an input to register path and we saw we saw what this means right there is some small violation here. Now, I want to see 5 worst paths starting from inputs simply do a max path it will tell me all the on the path. Now, I want to see let us say I want to see the worst case register to register path this is a bit tricky. So, what I could do is now here in this case there is no separate group of inputs and outputs all the. So, all the the path group here is a very powerful thing to have path group is always determined by the capture clock. In case of input to register path simply registers all registers are at the same clock it is always the the clock group is clock all the register to register path have the group clock all the register to output path since the output outputs are captured by again the same clock. So, for all the clock group is same it is the group clock. So, I can do something like a group path I can say group path I will maybe deal with this in a bit later. So, let us see what group path means first. So, this group path serves two purposes it will tell you how to it will may it gives you the power to create a new clock group new path group and in turn you could also control the optimization on this group path. Whenever you create a group by default you tell we see that I am creating this group because I want you to pay more attention on this you could do this for critical path also. This is this comes under infrastructure technique, but you could you could do this to create separate group right and you could use that those groups those path groups to report time. So, there is one more way to report timing on register to register path is by doing this minus from all registers minus to all registers. So, it gives some warnings ok it complains that you should have of what I will do is I would need some let me try one more example. Second thing what you could do is I will have to write a procedure for it that is why the group path is more sophisticated plus the the command report timing in DC is a subset of the report timing command in prime time it is much more powerful. So, when we come to the prime time we see that a lot of things work better there. So, the prime time design timing so the prime time timing engine timing engine means the the software that will do all the delay calculation and will show you the report timing before the prime time timing engine is much more superior to design compiler design compiler commands for timing are very basic versions of that. So, a lot of things we will see will start working in time that are not working here. So, I have to write the procedure to report register to register path that is why it is very useful to create group from the starting we will see that in the next lap perhaps. Now, we saw we saw how to report the worst path we saw how to report command to apart from timing report timing also tells what are the load and function number. So, we could do this and let us say we just do this so it is sure as a worst path again is the same path, but now it will start telling us what is the capacitance. So, here this is the capacitance this is the transition. So, if you see and what I will do is also also expand a bit and say it all only shows the input pins here and also show the those is only shows the output pins here the why is the output of each set. We also want to see what is the input pin and let us say we also want to see them in. So, now the report is much more extensive. So, it now there is an it starts with the with the clock. So, there is a clock here at P 1 clock we set the clock if you remember we set the clock transition number to be 0.5 it is coming here this is the net which has this cap this this net cap might be coming from the viral model. So, now C 1 to beta out this is the this is the this is the net now again. So, now you see multiple levels. So, collective on NAND cell we see that what is the net that drives it what is the fan out of this net what is the capacitance at this net we see. So, as let us let us see this inverter at the input A this is the transition this is the delay part instrumental this is the cumulative delay part this inverter input pin is given by this net which in turn comes from this memory right. Similarly, you could do this funny cell let us look at this AND cell. So, input of A 1 output is Y this is the net which has a fan out of 2 this is the capacitance these are the transition. So, the transition numbers are reported for both input and output pin the capacitance is only reported at the net which makes sense. So, now for example, this total cap this 0.87 might be it is the sum of the net cap itself the net N 2 cell plus the capacitance output cap at Y it is the sum of both right and. So, this is the net capacitance is are based on the viral model. So, this is the way you could report more extensive data using the report timing command. So, now I will request you to experiment the report timing command there are so many options available here to work with minus significant digits is one you could read more about it by doing the man page and you could try at least these options minus from minus through minus through there is also an option called minus path type. So, this is the option called minus path we could say N and it will tell us only the end points this is very similar to the report constraint report in this case it will it will give since we gave N it will give all the end points that are valid this is very similar to the report constraint plus it is not giving us violations now it is also giving us the path those are needed right. So, now when we apply constraint we want to check few things. So, there is a command for check timing. So, when we when I run check timing DC is telling it is checking few things and it is telling if there are any problems it is checking generated loss there are no generated loss we will talk about it loss when we continue this type it is checking combination loops it is checking input delay. So, it is checking so many things if there is then something absent if there is some problem then DC will tell you this design apparently right now it does not have any problems like this again check timing is much more powerful in prime time and well we will see a lot more of that in prime time. So, the aim of design compiler is to do a performance and area analysis performance and area analysis requires you to set clock 322 set area goals and you are done for most of the cases. We saw the report timing on when we do a report timing it gives us only the fitter path right. How to report the path we do a delay min this will tell you what is the hold now see the difference here it tells us delay min now this is the timing is coming from register to register path type is min which means it is a hold path. Now here this is the launch path clock comes at 0 this is the clock to queue timing and that is it goes to the memory spin something i1 21 pin. Now the capture is also at the same plot queue. So, the hold path if you go back to the figure and see the hold path is check on the same plotted the launch and capture is the same there is no concept of frequency here hold its frequency independent for max path for set up path it will pick up the path within maximum delay and the path with the maximum delay is bound to have lot of levels of logic. For hold path it will pick up the fastest path that is why it is also called the min path. Now for hold this is the launch path there is just a flop there is no combination logic there the capture edge is the same there is a clock concentrated now it will get added that means the capture edge will come later. So, capture at 0 adjusted for clock uncertainty point 3 the library hold time for this pin for this pin the library hold time is 0.2. So, this is the clock path the library hold time is 0.2. So, the data required time is 0.5 that means if the clock edge is coming at 0 the data should be stable till 0.5, but the data is getting altered at 0.2 till 0.5 the old data should have remain, but the new data is coming at 0.2 to the violation is 0.5 minus 0.2 to 0.2 0.2 itself and this does not depend on the clock frequency there is no clock frequency etcetera right. You will see a lot more of this in unit 5 please note that the for hold timing you should not be concerned about the hold timing in instances reports in most of the cases. There are very special cases where you should worry about the hold time, but as a thumb rule after synthesis check the area check the report constraints minus all validers and if you see violations analyze the set of paths. So, get about the hold paths for now. I summarize the report timing report again this is the clock launch this is the data path. So, this is the clock pin if you go first to the clock pin this is the data path. So, the first half of the report is the data path which at the end of it you will come up to the the data arrival time. The second part of the report is the capture path which is the clock capture path there will be adjustments for clock uncertainty elaborate set of time or output external delay or something like that at the end of which you will come up with a data required time. The difference between data required time and data arrival time if the slack if the slack is less than 0 it will show as violated if the slack is greater than 0 it will tell as met right. This is the way you interpret the report timing report it is one of the most important things you should learn for doing a good synthesis and for doing a good timing analysis right. So, in the next in the unit side you would see more on this probably I will have one more lab on this with some advanced synthesis techniques and some advanced usage of report time that would be a bit of an advanced lab. So, it will be very good to get your hands get hands on experience in the first three lines also please go and analyze the design yourself see what all design guidelines are not followed for example, if the inputs are registered if the output are registered and so on analyze that problem corrected and using the same library we saw that the timing needs at 300 about 300 maybe you should try and make this design work at 350 or 400 by doing some design changes if you can. So, that is a bit a significant assignment for you to follow. So, we will see more advanced features of design compiler of compile command and group path and so on in the next session. Thank you.