 Hello everyone, welcome to the third lecture session of the next slide in this session so last popular session we saw the concept behind it here why do we do SBA what is the need. Then we saw what is the SBA flow that we design data we make sure that the design is properly constrained and then we saw we saw last session we studied about the interconnect so interconnect is a very integral part of doing htg that is post layout that we did not complete without accurate interconnect data. Now in this session we will look up look more deeply into the clock and timing exception. So the agenda is we will look at we will have an overview of the clocks of all characteristics are associated with clocks we will see how the clock is specified. We will look at a couple of important terminology associated with clocks we will see what are generated clocks and then we will look more deeply into timing exception. Now most of what we learn about in this section should ideally be applied to synthesis example between synthesis and SBA there is not much of a difference when it comes to this what we discussed in this session but synthesis constraints are comparatively a bit more simpler when compared to study timing analysis this is because SBA is aimed at making sure that design works in all the operating corners and we want to make sure very very carefully that no no path is missed we need to make sure that all paths are covered all paths are properly considered and so on synthesis again is let us say let us say you have couple of clocks in your design they go through a MUX so you have an option of selecting which clock to choose for synthesis right let us say you have you have 100 minutes clock and 15 minutes clock and there is a MUX and you choose which which clock would you choose for your design you can have a choice business next in now when you synthesize it is clear that you would choose a higher frequency clock because we are concerned about the performance but for STH you need to make sure that design works for both the clock somebody might question that okay the design works at 100 megahertz it is supposed to work at 15 megahertz yes it is it will work at 15 megahertz there will not be any set of problem but what about whole there might so you need to also synthesize the path of the 15 megahertz clock to make sure that the design works at that in this specification you have said that your design will work on with the clock so this is what changes between synthesis and synthesis major concern the design should get the highest frequency possible you are not concerned about the DFP part as well in STH you are concerned about DFP you are concerned about all other test modes like like the chips we work on have number of test modes some test modes are dedicated for some interfaces and so on so we need to make sure that the chip works in all such modes apart from function so that is where STH becomes a bit more complex in terms of constraint points right so that is why these the commands similar commands in time-time will be much more powerful will have much more options than compared to the design compiler this is why we will though they are overlapped between SVA and synthesis but we will revisit all such commands and all such constraints when it comes to SVA and we will dig deep into it so so clocks we have already seen how to define a basic clock in design compiler the last we did all had single clock but there can be multiple clocks and a design definitely can have multiple clock in fact the chips we work on have some close to about 20 25 functions right for example if you take a take a chip for a mobile phone it will have maybe 3 odd clocks for for so many applications that a chip does so definitely we can define multiple clock that have different wave functions people see the there are 2 clocks 2 type of clock one is the virtual clock other is the real clock a virtual clock does not have a port associated with it and then a clock has 2 characteristics one is the delay network delay latency and screen we will see more of this and then we are coming slides the clock a clock can be either gated or generated a gated clock is one we saw an example of clock gating where power compiler will add clock rates to the line or in fact you can have in the RTL itself you can have some kind of waiting involved so design can have gated clock which is controlled by some enable signal it is very essential to make sure that both setup and hold constraints are verified on this gated clock or gating element in all probability would be a latch would be latch plus some combination element so they have to make sure that setup and hold constraints are met at this latch so prime time enables us to do that in addition a design can have the gated clock the gated clock are many times a design will have a plot based divider or some some counter based divider some gated gating logic based dividers there is a lot of top divider we can search the net for those there are a lot of top divider and divider in digital domain so a design can use those top divider to generate multiple frequency so prime time enables us to define those blocks then again the it comes to there is no characteristic called transition time so we can we saw this example we saw how to specify set lock function in design compiler it is not different in time time it is exactly same the only thing you need to now since now see now we are talking about X to A so we should also clearly be mark on the differences between pre-layout and post-layout in pre-layout you would define set lock function yes because you do not have actual transition number and since you do not want the analysis to be optimistic we will define some lock function number if we define about 300 PSM of an apps but post-layout we do not need to define lock function why because prime time has all the characteristic data and we discussed in the last session that every node whether it be a data part or a block part prime time will calculate function so post-layout the transition numbers are accurate we lay out the transition numbers are estimates so post-layout you do not need to define let us look at the clock specification this we need to tell prime time at what point we are creating the clock what is the frequency of the clock in terms of period then we need to tell prime time what is the duty cycle time we may choose to tell the duty cycle or you may choose to tell the there is an option called edges and waveforms so there are multiple ways in which you can define the clock we will see some examples this is the basic clock specification now we figure on the right hand side something called system lock so now we need a clock of this type which rises at 0 falls at 5 and the period is 20 so we map this to the command create lock minus name system lock now this is the port this is the this is the clock name which can be anything and this is the port of the design period is 20 as given from the diagram and waveform is 0 5 waveform the first digit means rise the time at which the clock rises the second one mean the time at which it falls now let us say in this case what if I do not give the waveform if I omit this what the PT will do it will create a clock of period 20 and it will create a clock of default 50% duty cycle that means it will rise at 0 and fall at 10 it will do something like this so if you choose to omit waveform then please make sure that please be reminded of that it will create a 50% duty cycle clock by default now we will see some advanced some some other options of create lock so now let us say you have this is a JTA clock so many times the test clocks are slower but they are not a 50% duty cycle they can have waveform such as these where so now in this case this this is a comparatively complex clock this period being 1.2 this is the period and in this period it rises and falls twice right but it repeats periodically after 1.2 so this is test clocks can be like this so this is not not a surprise but although the function clocks are not like this because you would typically want one active edge per clock period but the test clocks can have this kind of people so how do we define such a complex clock first thing you tell what is the period second thing the waveform waveform now you define the waveform rise at 0.3 fall at 0.4 again rise at 0.8 fall at 1 and it repeats in a period of 1.2 this is the way you define the complete specification by using the waveform switch so you can explore you can see the man page of the clock there are lot many options you can try out in fact there is one more command created clock which we will see later it has more options and create but these are the two most famous applications of the clock first you give the period most important then you define the waveform and then you tell what for the clock after the period now let us look at a characteristic called clock latency now clock latency is so when you define a clock on a clock forward that clock will fan out to a number of thousands of it is right so pre-layout time time does not have any information of the clock network so what it does pre-layout it considers the clock to be ideal by default ideal means that the clock will reach all the clock at the same time and if you do not give anything it will reach at 0 line there will be no delay but the only delay will be if any of the if any of the for any of the buffers included in the clock that is all there would not be otherwise there would not be any delay that too in ideal clock mode prime time does not consider any clock that would be whether there will be buffers or biode model whatever prime time will assume every clock gets the clock in zero time right to make sure if you want to implement if you want to estimate and apply any clock latency there are two types there are two ways right first is for post layout this is how post layout we can either allow prime time to compute latency by propagating the delays along the clock network this is accurate but it is only applicable if you have accurate parasitics and then you have accurate parasitics only after the design has been placed in the bulkhead right so we will see this we will see this example of this in the lab also second way is the estimation which is for the pre-layout part so we can estimate and specify explicitly the latency of each clock we can specify this latency on individual ports any register clock pin in the transistor fan out transistor fan out means all such registers which on which this particular clock reaches are affected and overwrite any value set on the clock update this is typically used before clock resynthesis we will see an example of this so this is an ideal clock for example so this is a clock source this is the clock source this is PLF now let us say this is the chip I am working on right this is and I am doing HTA for this this boundary here so there will be a PLF I will define the clock as the output of the PLF this is typically the case but let us now consider this design let us say you are doing that the HTA of now this boundary which does not include the PLF so what we do is we will define the clock at the port we define the clock at this port now a latency has to there are two types of latencies first is a network latency that means the network delay the delay the time it takes from the clock definition point to reach to all the design this is for network latency for an ideal clock if you do not give anything the network latency is assumed to be seen the source latency is the one is the delay between the clock definition point which is the port of a design and the real clock source if you know about it the real clock source on this the clock will come so in this case we know that the clock will come from a PLL it will reach this clock definition point in some amount of time this is called source latency now for STA purpose now let us say so this was for the on chip clock source let us say you have an off chip clock source this is very common for any interfaces like IPC or SP or there are a lot of chip level interfaces on which the clock will come where it comes from either a different chip or from a different or from a also this is situated off chip so in this case also things remain same the clock source the the time it takes from clock source in the clock definition point is called source latency network latency is what is inside the design so you can remember it this way network latency is the latency which is within the scope of a design source latency is something which is outside of a design now this is these are the commands which you use to define the source latency and network latency by giving minus source the minus if you do not give anything by default it is supposed to be a network latency now what is important what is not now many times we do not give any source latency many times why because first of all we are let us say I am working on this design at the bottom now many times I will not be worried about the source latency because the source latency by default I mean in most of the cases it will not update the timing analysis of the design we will understand it why when we progress through this but but network latency now what network latency represents is see the network latency is an estimated value it is not an accurate value right when you talk about when we set clock latency also please know that set clock latency is for the network part is only used for pre layout for post layout right and actually calculates all the numbers because it has all the data so when we apply the estimate of network latency usually in when I do SMA I in most of the cases I do not use the source latency or network latency source latency why I do not use source latency is because many times I do not have any estimate and let us say a source latency a uniform source latency of x will not affect the results of my coming to network latency now network latency becomes important in the case where lot of all the flaws in your design will not get the clock at the same time they will get clock at a different point of time this mimics the clock three synthesis data so what clock three tries to achieve in in in back end it will try to make sure that the delay the absolute delay I mean so let us say that thousand blocks on which the clock will go it will make a buffer tree it will make a problem and the aim is to make sure that the clock reaches at all the register in a very tight window so the absolute difference between the latest arrival and the earliest arrival is not huge let us say for I could say that I could tell my back end but please try and make sure that the clock so this is what blocks you the maximum difference between the two registers and the difference between the maximum arrival and the minimum arrival is called the clock skew so that the aim of the clock three synthesis is to keep this skew going now you can you can use network latency how you can say that set clock latency so in this case there is in this case you can use a you can use it without source or with source the effect is same so the other thing that mimics this process this skew is called clock uncertainty we will see about that in the next slide so but please be careful while using the source and network latency you should know what actually and what what does not affect if you give something like this set clock latency minus so get off this clock and you have only one clock in your design then it does not make any difference to a timing analysis however if you do something like this minus early and minus late this will make a difference because now the values are different now let us see what prime time does so if you give minus early and minus late options so what what prime time will do is that from the idle clock without so the top waveform is the idle clock without any clock latency so the waveform is 0 and 5 now it will apply the early value plus 1.5 so it will delay the edges by 1.5 each this one this one and this one and then it will create one more clock in time which is which is delayed by the late value and now for setup analysis what it will do it will launch late and capture early launch late and captured early what it means is that it will take the case which is most pessimistic which is most restrictive so it will assume that for setup the launch clock will come as late as possible and the capture clock will come as early as possible now see the difference between early and late is 1 nanosecond and so it is 1 ns here and 1 ns here so it will shrink your clock period by 2 ns because you are delaying the 1 edge by 2.5 and you are launching late and capturing early for both it will do the other way round whatever is most restrictive for hold it will launch early and capture early so this is this is the hold it is a hold is a 0 cycle thing so it will launch early and capture early right so please be careful in using this early and late figures you should be very sure that what is the application you are trying to what is the what is the specification you are trying to implement now second is the case where you have actual parasitic data in this case you probably most of the cases will not need a setup latency command unless until you want to implement something that is off chip and that has an early and late value so still see still when when when you have actual parasitic still this is the part which you cannot get implement accurately because this is something which is off chip so you need to still again based on you need to write commands based on some specifications which are already available to you or some of the and only when you have a different early and late one so when you have actual parasitic with you a prime time in an accurately determined clock latency that propagating the clock through the network this is highly accurate analysis and the command to do this is that propagated clock so you define the clock you say create lock you say create lock CLK minus meter minus waveform and then say that set propagated clock only when you give set propagated clock time will start the actuality without this without setting propagated clock it will read your clock as ideal so this is now something special and different from synthesis so if we have written parasitic data if we have defined a clock and not given set propagated clock your analysis is wasted so this is one extra command that you need to add your constraint files when you go from this is one of the most important common clock uncertainty is something that is a command that helps us in limiting the clock skew that comes as a result of the clock. Now what what clock uncertainty does that we apply the uncertainty minus there are two options minus set of minus one you can if you do not apply this option the same uncertainty value is taken from the set of. So we define like the clock uncertainty let us say in this case we define a 0.2 value for set of and 0.05 value for which on a particular clock what this will do is that it will for set of check it will subtract 0.2 from the capture edge so it is again taking which is whichever is in most present state. So uncertainty means that the capture edge can come in the late by this value or earlier by this value for set of it will consider the capture edge to be coming earlier because it is more effective and it will reduce your slack. So now for set of it will capture here instead of earlier for set of without any uncertainty it would have captured here now it is capturing here right for hold earlier it would have been capturing here in fact not this is hold would be the same as it would be capturing here or now we can take here because both are the edges are same now it will capture later which is more restricted for hold. So clock uncertainty the value will decrease this amount of slack you know now. So when you apply uncertainty from between two different clock domain it is called input clock uncertainty the command is same the only difference now here is that earlier you gave just it will give just single clock without any minus from into option this identity is called intra clock clock uncertainty if you say minus from to some clock then it becomes a interclock uncertainty right. Now important points really out has ideal clock what it means is that S T assumes clock arise at each clock at the same time in this case we have to apply we should apply some clock uncertainty what values do we apply the clock uncertainty for three layout should be clock three skew plus the energy term clock three skew you will get from your back end from the person who is doing back end it is a it is a function clock three skew is a value which you give to the back end skew and if we try to move the clock skew within this range. So you should you should ask this or you should search if you do not do back end yourself you should ask the back end engineer for this value and you will provide if not you have to estimate it you can take it to the 200 years of time the clock specification PLL jitter is the case where the clock comes from PLL and it is the spec of the PLL right for example the PLL might have a 25 years this is very important. So please do not whenever you do synthesis or you do PLL out STA do not forget to apply clock uncertainty because otherwise you are not capturing the set of the clock skew which will come into place after the back end has been done for force layout now force layout you know this you go need to give this why because the clock three is accurately captured and time-time it calculate all the delay. So but PLL jitter is still available is still there PLL jitter has not disappeared or it is not being calculated PLL jitter is a function of a PLL it comes from the dot length of the PLL and you should always apply this. So for example three layout let me give you some values for both parity three layout I can say that my clock three skew would be 300 PS and let say my PLL jitter is 25 PS. So my three layout clock uncertainty would be 300 plus 25 325 PS when I go to force layout now I know that my clock three skew is taken care of when I set the propagated clock but PLL jitter still is present. So I will set my clock uncertainty to be simply the jitter value which is 25 PS right okay clock uncertainty has one more application it is very popular. So let us say you are doing synthesis now and you as your target frequency let us say is 400 megahertz but you have a doubt in your mind that okay whatever values I am applying the amplitude values are now I applied some I applied the clock frequency now but you want to oversynthesize the design for some reason right for some reason you want to experiment that okay I am not sure that okay the design I am synthesizing a 200 but in backend due to some mismatch between the backend my synthesis or due to my valid model not being accurate enough I need to have some margin in synthesis. So what you could do they are two choices one you can increase the clock frequency for synthesis you can let us synthesize it 450 megahertz or you can apply an extra clock uncertainty. So extra so any number you apply in clock uncertainty will reduce that value from the clock frequency for set up chip right and in design compiler in synthesis we are worried about the set up because it affects our performance. So we can we can use set clock uncertainty to give us some margin in synthesis right this is a very popular application of clock uncertainty but this the slide here gives you a very good idea of what values to give in figure out and post out okay now now let us come to generated clocks. Generated clocks are based on master clock can have a generated clock can be generated from either a master clock a primary clock what we call or even a one more generated clock. So you can have generated of a generated clock it does not require any additional constraints it means it means that it does not need to be we do not need to apply any clock latency and uncertainty because everything will be derived from the master clock itself start point of the clock path is a master clock definition concept this things will become clear once we do the lab these these two statements. So in what cases do we do generated clock one is one of the example is a divider clock divider now this this logic is nothing but a clock divider the Qn is fed back into D or if Qn is not available inverted Q will be fed back into D. So at every edge of at every active edge of clkp clkp div by 2 will be a divide by 2 clock of clkp right. So clkp is a master clock like this like this and every active edge that means this positive will generate this this edge this positive will generate this negative edge because inversion happened and fed back into D. So this is the clkp div by 2 is a divide by 2 clock how do we define. So if you do not do anything what prime time will do is that it will trace you define a master clock here and prime time will simply stop here it will not do anything. So all these clock points will be without clock if you do not define a generated clock because prime time by default will not go through a sequential element it goes to a combination element but not through a sequential element by default the other default variable. So you need to give a generated clock name this can be any strain source is the master clock source which is this point wherever master clock is defined and we said divide by 2 and where to create it in create clock the where part is either a pin or a port again in create generated clock the where part is the either a pin mostly it is a pin and so you you tell that you tell prime time that I have a generated clock which is with this name which is generated from this source created at this point and the relationship is divide by 2. Now this this strain here divide by 2 should match your netlist functionality also this is very essential then the matching of the command the created clock command and your netlist structure the functionality of a netlist is very important. If there is a mismatch then prime time will not be able to calculate this delay. Now see now see this let us say this you define some latency for this law. Now what is the latency of a divide by 2 clock the latency of divide by 2 clock is the latency of the master clock plus the latency of the path the delay of the path from the master clock to the generated clock right. If there is a mismatch in the in the in this strain divide by 2 for example and the functionality let us say you do not you say divide by 2 but the register there is no register here there is some buffer here. In that case there is a mismatch and prime time will not calculate the correct clock delay right. So, it will also give a warning we will see what warning is that. So, you should look out for these kind of warnings and make sure that your you do not have any such warnings which tells you that there is a mismatch in that means clock definition. Now generated clock there can be lot many examples of generated clock we will see few of them there can be a multiplied clock. So, there there can be some logic which multiplies the clock. So, instead of using a divide by you can use a multiply by rest all options remain same you can have a gated clock in the sense that. So, in this example the 6th clock is gated with SC control and a core clock is generated. Now in this case there are two states whether this clock core clock is off or on right in SC you are concerned about this state on we are not concerned about the off state right we are assuming that core clock is present always. So, you do not need to worry about the SC control model you just need to specify a clock here at core clock and say that this clock is just a divide by 1 that means the waveform here at this clock and the base form at core clock are both same divide by 1 tells that. So, you can even have a divide by many time we have a case like this we have a clock define on the input port and we create a generated clock at this point which is the output of a buffer. So, it is a very useful application when you do more SC when you become bit more experienced in SC you will probably appreciate the divide by 1 functionality. So, it is a very popular application using a divide by 1 clock. So, this is how you create it let us give divide by 1 and. So, divide by 1 should not have any clock involved right because whenever there is a clock involved usually the division is more than 1. So, division factor is more than 1 it is either 2 or 4 or something like that. So, whenever it is divide by 1 it means that it is going through a combination of it which does not include any mean PDET division. Okay, let us now this is one case where we do not use a generated clock, but this is why because there are 2 clock that are generated generating a generated clock what it means is that there is a clock sysclock here there is a core clock here and ending of these 2 is generated in the main clock. So, sysclock core clock when we and we get this kind of a waveform. Now, we could we could create a generated clock here, but it would not be this it would not be it is not recommended because it is generating of 2 clocks sysclock and core clock. So, in this case it is just a create clock, but the only problem is that when you do a create clock here all the latencies behind this that is these all the latencies are not taken into account. Any create clock means whenever you tell prime time it is a create clock at some point all the latencies before that point at this point only the latencies which are proceeding from that point are calculated. When you do a create generated clock all the latencies leading back to the create clock will be taken into account. So, you have to be very careful in such cases this also depends on what is the relationship between main core and sysclock are they synchronous are they synchronous they are what is the what is the nature of the timing path between them. So, this is a one particular example, but it does not mean that you create clock every time you see this kind of a logic it completely depends on the type of a dependent right. There is one more option. So, these examples we saw that we caught the use of divides by and multiply by options. The more popular is the edges option edges option clearly tells prime time what are the edges being used in the great genetic law. I would recommend using the edges whenever you can I prefer edges over divide by I will tell you why let us let us see this to these cases. Now, let us say you have a you have a clock master clock DCLK here. Now, there are 3 clocks here we have 0 clock DCLK div to pH 1 clock. Now, at Q we know it is a divide by 2 clock, but now DCLK is inverted what it means is that instead of positive edge generating the clock now it is the negative edge that is generating the clock. So, let us see the waveforms. So, this is this this is the negative edge this is the negative edge this is the negative edge and generated clock generate divide by 2 clock is now generating of the negative edge. So, this negative edge we call this cos edge this negative is cos edge will cause this negative. So, DCLK divided by 2 is generated of the negative edge of DCLK. Now, in this case if you want to give a give a divide by 1 prime time will give an error because prime time finds that divide by 1 sorry divide by 2 to here prime time will assume always assume that it is the positive edge that is generating. So, in this case you have to give you have to tell prime time in some way that negative edge is generating the clock. How do you tell that you forget divide by 2 option you use the edge is amount. The edges of the master clock are numbered like this 1 2 3 4 and you tell prime time that DCLK div 2 the rise edge comes at 2 the fall edge comes at 4 the next rises rise edge comes at 6. You have to give at least 3 edges because this will define the complete period rise fall and rise combined together these 3 edges define a complete period of the generated clock. So, this is what you do created in create generated clock minus name edges 2 4 6 1 3 and 5 are positive 2 4 6 are negative. So, now prime time knows that negative is being used to generate the generated clock. Similarly PA PA 0 clock is anand of the master clock and the divide by 2 clock. So, this is the ending logic. So, it will generate this kind of a clock. Now, now looking at this waveform now looking at this waveform PA 0 clock you can easily define the clock what are the edges 3 4 and 7 right for pH 1 clock what are the edges 1 2 and 5. So, now a job becomes very easy you know your design you can draw the clock waveforms what is needed you know what clock waveforms will be there and then just translate that clock waveform into a and define a generated clock. This is the most is the best way to define generated clock. This will leave out any ambiguity about which edges generating which edge of master clock is generated generated clock right. Again this is the case of the clock the inverted clock. So, in this case the clock is inverted. So, in this case also I would recommend using edges option there is one more case which is one more way you could do that you could say divide by 2 and add minus inverted. So, this tells that instead of ok. So, non-inverted version would look something like this, but there is a inverter here. So, you can tell that you are not you are defining the clock after the inverter not before the inverter before the inverter the situation will remain same, but when you are defining after the inverter you can say minus invert and prime time and understand, but again I would recommend using the edges option. So, generated clock latency already talked about in the sum of. So, this is the generated clock this is a network latency the latency here is the sum of the generated the source latency from master clock to the generated clock and plus any source latency that your master clock can have right. So, it is it is simple this is the exercise I leave for you there is a sys clock here assume any waveform here assume a 100 megahertz 50 percent duty cycle and now tell me what tell you write down on paper do this offline. What is the what can be the create generated clock at div 2 a and div 2 b at these two points write the create. So, first write the create clock command for sys clock then write the create generated clock command for div 2 a and div 2 b right. So, just please be careful when you please be careful with the polarities. So, what I try to include this in the lab I try to answer this in the lab, but it is very easy you can do it yourself. Now, let us talk about let us go deep into how time time evaluates set up and hold edge it now next three slides if you understand next three or four slides you will have no problem whatsoever in understanding understanding any kind of report timing for any clock latency right. So, whether you have multiple clocks or single clock or you have very complex clock network any such case if you the query in next three or four slides would guide you in understanding any time report any complex time report right. So, many people in the industry are also not very comfortable with this, but I try to explain right in detail. Now, by default assume you have a single clock this is very we have repeated this in time. So, what are the set up edges the clock at ff 1 and clock at ff 2 are same. So, we have not so this is by default the edge at which data is launched on ff 1 and the edge at which data is captured on ff 2 are one clock period apart for this is the default. Why because you want any data launched by ff 1 to be captured by ff 2 after single cycle this is the default behavior and the same edge at ff 2 now see clock are same. So, these two edges are same right this edge is one clock period apart, but these two edges are same you just have copied the clock at ff 1 and ff 2 to show you clearly. So, this edge the same edge is used for hold why you want to make sure that any data launched by ff 1 on a particular edge does not disturb needs the hold timing at ff 2 right the same edge does not disturb the hold timing at ff 2 this is why the default behavior set up is called a single cycle path cycle 1 hold is called a 0 cycle path why set up is checked after one clock cycle hold is checked after 0 clock cycle that means, hold is checked at the same edge this is a very simple case. Now, let us come to a case where you have multiple clock and now we will try to and try to explain the general theory on which SCA tool like prime time operating right. For set up analysis prime time let us read the statement prime time looks at relationship between the active clock edges there is a keyword here active clock edges over a full repeating cycle when does a cycle repeat itself now this is the statement is common to a general case of the launch and capture cycle a clocks being different equal to at least the LCM of the 2 clock periods for each capture edge at the destination flip flop PT assumes that the corresponding launch edge is the nearest source clock edge occurring before the capture. We will go to the figure and we will keep toggling between 2 slides of this statement and the figure and the diagram and we will try to understand it. So, the important thing here is that active clock edge it will analyze for the period for the LCM of the 2 clock periods let us see a figure here. Now, let us say you have 2 clocks now I have separated out the clock 1 and clock 2 are different the first clock is 10 0 and 5. So, the second clock is 25 5 and 25. So, we have complicated stuff here now there are 2 clocks you do not have 50 that the clock 2 does not have a rising edge at 0, but rising edge at 5. So, first you you should understand you should try and map the command with the clock waveform it always helps to to draw waveform on paper. So, create clock period 10 rise at a as a 0 this is the time scale rise at 0 fall at 5 period is 10 second is 25 period, but rise is at 5 fall is at 12.5. So, this is now prime time. So, we have marked the activities first keyword first keyword active first what you do you mark the activity. So, this is where we have marked the activity here and here. Second keyword least common multiple of 2 clock period what is the least common multiple period 10 period 25 the least common multiple is 50. So, we will draw the time scale till 50 right and we will analyze all the active edges as the idea. Third important point for each capture edge at the destination fifth clock clock 2 is the one that is capturing rate on there are 2 capture edges there 1 and 2 right what is the set up check here for each capture edge we look for the launch edge which is just before this capture edge just before not in the same time what we we treat we see this capture edge one what is the launch edge just before this this is the launch edge. We go to second capture edge why we are analyzing this capture edge also because it lies within the LCM of the period for this capture edge the launch edge is this. So, this is the set up check in this case there are 2 set up checks set up 1. So, launch will be at 0 capture will be at 5 set up. So, there is a in first case set up 1 there is a 5 and a 0 and 5. Second the launch is at 20 the capture is at 30 the difference is 10 what is more restrictive 5 you need to meet set up the combination logic plus the delay of the flip clock 1 plus the set up time of flip clock 2 everything should be less than 5 there 2 cases should be less than 5 should be less than 5 prime time will check for 5 because it is more effective right I will repeat this again keywords active clock edge. So, you first of all you map the command with the waveform or you draw the waveform first then write the command that the logic can be mark the active edges. Second keyword LCM of the 2 clock periods you draw this you draw you draw all the active edges within the LCM LCM is 50 here. So, that is why time scale is from 0 to 15. Third you mark the capture edges at the capture clock. So, we mark the capture edges at at flip clock 2 now we look for the launch edges that occurs just before the capture edge just before not at the same time. So, here f of 2 captures at 5 what is the launch edge just before 5 it is a 0. So, one check is from 0 to 5 other check is from 30 to 20 take whatever is the restrictive 1. Now, do we need to do this analysis ourselves No, we do not need to do this, but we need to understand this is how prime time that is coming. So, now let us say I have this design and I give it to a new guy who has who has not understood this case, but who has only studied this case this type of simple case. Now, we will apply this same concepts here right and see that will matter of the clock is same. So, what is the LCM? LCM is just this one 0 to 10 because both on both sides the clock is same we we mark out all the active edges. Now, at so what is the capture edge this and this what is for capture edge 1 what is the launch edge just before it this one happened in the past. So, there will be some as here not at the same time for capture edge 2 what is the launch edge just before it this one in this case both have same both have difference of 10 that is why set up this there in this case we set up is of single cycle right. So, you can apply the same concept any any cases now. Now, the idea of understanding this is this is how prime time operates and many times when the when the clocks are complex when there are multiple clock and they arethere are different parts between among such clocks it is very important to understand this to make sure that you understand the timing report. So, this is how timing report will look like it will say clock 1 launch at 5 launch at 0 clock 2 capture at 5. Now, you should understand where the edges 0 and 5 come from right sometimes they are negative numbers involved. So, you need to understand where the negative number is coming from right. If you understand this you will you can use this to write proper and accurate exceptions you will talk about timing exceptions later you can write use it to write accurate timing exceptions later on right. So, it is very important to understand this now we have understood how prime time will calculate the set up edges. Now, let us go to the holding hold is writing more complex have some patience the hold leg again we will switch toggle between the two slides first principle of hold you should complete the set up and you should understand what is the set up edges what are the set up edges. Now, let us go to hold hold relationships are based on the clock edges adjacent to the ones that are that determine the set up relationships. So, first broad way form do the exercise method to determine the more restrictive hold what prime time will do I will not read out the text, but I will I will point out the rest of that. Now, consider this this set up edge one right we need to consider all set up edges right 1 and 2 here 2 cases here. Now, in this case prime time needs to make sure that whatever a data is being launched here does not disturb. So, what it assumes is that this edge here this particular edge here is capturing the data length by this one right the FF 1 CLK and FF 1 at 0 whatever it launches data at 5 the data is captured. So, it needs to make sure that whatever data is launched at 0 does not disturb the hold edge at the active edge which occurs before this set up edge. That means, it needs to maintain the hold relationship for the capture edge that occurs before 5 set up is captured at 5 the hold should be met one cycle behind always hold is one cycle behind set up by default set up is a single cycle path hold is a 0 cycle path set up 1 hold 0 hold is one cycle behind set up. If this is set up between 0 and 5 the hold will be 0 and in this case that edge will be somewhere in negative right fine we noted down again for the same edge it will do the other way round. Now, it will check whether the next the edge which is after the launch edge that is this edge now does not disturb hold at 5. So, it will first it will take. So, the formula is first determine the set up edges then check hold for set up minus 1. So, that this capture will remain same you check for set up minus 1 to capture set up plus 1 sorry you check from set up I will write this down later. So, the first formula is launch minus 1 comma capture this is what we have been learning this is this is launch and we check between launch I will clear it I will write it down. So, first you mark the set up edges then between launch and capture minus 1 this is the launch edge for set up this is the capture edge for set up we check the relationship between launch and capture minus 1 which is somewhere in the negative. Second test we do is we do for launch minus 1 to capture this is the case or I will just correct it sorry launch plus 1 and capture. So, second is we do launch plus 1 and capture. So, what is launch plus 1 launch plus 1 is this edge what is the capture edge here same. So, hold 1 a is between launch minus 1 and capture launch minus 1 and capture minus 1 hold 1 b is between launch plus 1 and capture. Similarly, we do it for 2 hold 2 a is between launch and capture minus 1 hold 2 b is between launch plus 1 and capture right. Among all these cases prime time it only report which is most restrictive what is most restrictive hold 2 b why because the edge that is same 0 0 0 is most restrictive or in some cases what can happen if the launch edge is before the capture edge or hold that can be more restrictive, but in this case I guess hold 2 hold 2 b it would be most restrictive. So, anytime you look at 2 blocks you first determine what are the set up edges second you determine what is the hold edges why do you need to do this you need to do this understand the report time report. We when we define the clocks or any any any multiple clock in number of multiple clock prime time will do this for you automatically, but when you look at report timing you should understand how prime time came up with it correct or not many times by looking at the report timing you will know that oh my clock definitions are not correct I need to correct them right. So, this is this is how first you understand it and then you apply these concepts to understand the timing report and then you can verify that whether your generated clock definitions are correct or not right. This is an exercise we will try to do it in that also consider a master clock consider these 3 generated clock generated clocks 1 2 9 5 6 20 1 2 5 and now tell any now calculate what are the set up on edges for the case where data is launched by clocked and captured by clocked right. So, I will also recommend reading the prime time manual if you have access to it it will explain this in much more in some more detail, but this is the text on the slide also is good enough I will actually use the prime time manual itself to explain the concept. So, you can remember this formula set up is easy you first mark out the capture edge then look out for the launch edge others just before the capture edge mark out the set up for the LCM part for hold you have these 2 formulas launch and capture minus 1 launch and capture you do not need to mud it up once you start understanding these concepts you can understand any time. Now, virtual clock what is virtual clock virtual clock is something that does not have any fixed port in the design it is kind of a floating clock and it is mostly used to define input and output delay for example. This is one example where there are 2 virtual clocks define virtual clock trading and virtual clock here some period we create a regular clock period 10 and we can use this these virtual clocks to define input delays or output delays on some codes right. So, this is the slide just captures that you already studied that ok. Now, we are we are let us look at exceptions what are exceptions first and then before this let us say if you do not know do not know about exceptions do not apply an exception this is what prime time will do by default whatever we have understood till now. Prime time it will break your whole design into timing paths it will assign various path groups based on the capture clock to all those timing paths if you have multiple clocks it will use this logic to arrive at the launch and capture edges for setup and hold right and if you have multiple clocks it will assume that if you do not give any exception it will assume that all clocks whether they are whether the whether the period have LCM limited LCM or not it will try and it will assume that all clocks have path among them. Now, let us look at this this case and see and work out a case where a clock first clock there are 2 clocks first clock has a period 22 and second clock has a period of 31. Now, you say man the LCM is pretty big mom both are odd number both are prime number 7 into 31 that the LCM is pretty big and you and so for such cases if you look carefully to think carefully such cases are not logically possible that is that if there are 2 clocks whose periods are not a integer multiples or some some rational number multiples of each other with limited LCM then that design is not you cannot have 2 clocks with period 17 and 31 and have paths between them in all probability when whenever there are 2 such clocks with the period not multiple or to be multiple of each other then in all probability all the paths between such clocks are to be found right they are asynchronous clocks. So, you have so many times I will tell you a case now let us say you have a you have a chip that is for mobile phones and it has a CPU which works let us say at 1 gigahertz and it has a video for let us say that works at 330 megahertz for example. Now, the CPU part will work independently as the video for right. So, you have 2 clocks 1 is the CPU clock or there is a video clock. Now, they do not have a relationship between the CPU clock is working in the CPU domain and video clock is working in the video domain, but what may happen is that the video domain might be based on some condition it might raise some interrupt to the CPU domain. So, what will happen now in this case the video clock will launch the interrupt and the CPU clock will capture the interrupt, but it is not expected that such a path will meet the regular and set up whole set up whole time. Why it is not expected it is not expected because the clocks are not possible of each other and proper multiple sufficient and we have not designed it like that and it is not necessary to design it like that. Interrupts are mostly one time occurring signal they do not toggle every time every clock cycle. So, you can you can choose to not check any set up a whole time on that. There is a completely separate design concept which you might it might become clear in some other course based on or digital design, but these cases are normal. So, in this case if you do not give anything if you do not define in time expression prime time will assume that it will do all such sorts of calculation. It will launch data at video clock and it will try to capture in CPU clock and it will use all such principles to define set up a whole schedule. Now, do you really want that no. So, for cases where you do not want prime time to go on with this regular timing calculation techniques you can give certain commands to override those and to make your timing algorithm more accurate. Such group of commands is quite timing exception. These are the list of commands that come under the category of timing exception. Set case analysis, set disabled timing, set fault path, multi-cycle path, set noise to the second delay. We look at each of them in some way. So, just remember what is the timing exception? Timing exception is any command that will force time time to override its default behavior right case analysis. Case analysis is a way of specifying given mode for the design without altering the network function. You can specify for current time. So, what is the typical the most famous example? Your chip your design has two modes functional and scan. So, it is a very common thing. The scan path will sensitize the path which are between the scan input and the data pin of the path. Without it will bypass the combination of which is the scan chip path right. Now, if you do not do anything in a particular session you will see both the function and the scan path the scan chip path and you do not want to do that. You want to separate cases. So, in such case what you can do there will be a thing called scan enable or test enable or test mode or something like that. You can set a case analysis of 0. When you set a case analysis of 0 and such a thing the design will enter function mode. So, prime time will calculate these type of calculate the days assuming that scan enable is 0 or scan test mode is 0 and that means it will only worry about the function mode. So, any such case scan test mode right signal typically it would mean that if you set 0 on this it will switch off all the the paths which are from scan enable to the next data problem of the path. So, but the net instruments say you do not need to you do not need to make any modification immediately. You can just use such case analysis to tell prime time that ok I want you to analyze timing assuming that this signal is 0 or this particular signal is 1 or this particular signal can only rise this particular signal can only form these are 2 examples right. You can say that set case has 0 or 9 1 you can say that we can set a rising case analysis on we spin we spin which means that there will not be any fallage here. There is one example at the end of the session which we make it is clear when to use a case analysis, but this is a very powerful tool command and it is it is a very popular command. And most of the times the most practical functionality the most popular functionality is to assign different modes for STU. You can have one mode for function one mode for scan one for some other test mode and use in such case analysis appropriate case analysis on the controlling pins. Second is false path. So, I was discussing a case where there is a video call and there is a CPU and there is an interrupt signal and you know one time time to check the setup mode between these two domains. So, what you could do is you can tell prime time set false path and you can set the false path on this interrupt signal. What it will tell prime time? It will tell prime time do not check any timing constraint on this signal right. So, it will not check any setup or any pull on this particular signal which is what we know. So, by definition false path is the logic path that is this path that should not be analyzed whatever case we were talking about. So, idea keyword it exists the path exists, but should not be analyzed for time. So, for example, a path can exist between two multiple closet blocks that are never selected at the same time. So, if two blocks and only one is selected at one time. So, any path between these two blocks is not valid. This is one example where we are setting a false path from a register to some register. You should be careful about what we use then from what we use them to. Remember for a register to register path path point is always be locked in and capture is always a data point. So, you should be careful in from path they always should be a if you are talking if you are mentioning a path start point. So, in from you should always mention the clock point of the register. In capture if it is a plot you want to you want to set the false path on. So, minus 2 you should always mention the data one of the one of the other they don't. So, if you set so it should always be very specific it should always be very specific to avoid any errors right. This is very dangerous both all timing acceptance are very dangerous. If you give a wrong command and it is accepted then it is the most dangerous solution. A typical chip can have hundreds of false paths and it is a difficult task to debug that if you have given any wrong command and it is accepted. So, for example, if you by mistake do a SFB3 and it is a valid flaw. So, it is a wrong timing exception timing will not be checked and in my experience any timing that is by mistake not checked will most probably violate on chip and you will have lot of problems in debugging on silicon. So, timing exception also so any time failure debugging on silicon it is very very difficult right. So, please be careful when you apply a false path right. False path is mostly used to define clock relationships. So, in so one example I told you that you can set a false path on the interrupt system from video call to that goes from video call to the ctl. Now, let us say apart from interrupt that 10 more signals that go from video call to then let us say 10 interrupts that go from video call to ctl. Now, in this case you have to write 10 false paths right to declare false path on each of the each of this path. Second better way second most of this people in a better way is to tell that all the paths from video call clock to CPU clock are false. So, this is how we define the clock relationship. Ideally let us say your design has 10 clocks if you do not do anything prime time will assume that all path between any two clocks are valid. So, it will produce timing reports for the same you can tell that for any two asynchronous clock you can tell like this. You can say that false path from clock point to clock 2 and it is also essentially do the other way around from clock 2 to clock 1. Paths from video to CPU are false path, but there might also be paths which are from CPU to the video and we also want want them to be false path. So, you need to give two false path from clock point to clock 2 from clock 2 to clock. There is also one more way of doing this CPU data. So, false paths are most popular to define clock relationships. Now, it is disabled timing again it is a it is a less popular way of doing things because people will use false path. So, in a particular situation in fact, you can apply any of any of the things you can apply in the pivot timing or you can apply k-pan or you can apply a false path, but you should do what to apply then some commands work better for some cases. For example, for defining clock relationships that false path works best right for putting the chip into a particular mode like power function or some other text mode case analysis works best. Disabled timing what it does is that it will disable it will remove the time now let us say I say a disabled timing from pin A to pin Z of a particular answer it will not even consider that path. False path is something different false path the path exists time time will do the delay calculation. So, only thing it would not do is it would not check the set up and hold function. Disabled timing it removes the affected objects from the delay calculation itself. So, when when should you use this if all the paths you should use disabled timing only if all the paths through a particular pin are false remember pin it is pin based. False path can be between 2 clocks, but you cannot disable timing there you cannot use disabled timing to define the clock relationship. You can only do disabled timing only if all the paths through a particular pin are false. You probably might see some of this I might use disabled timing in one of the labs I am not sure about it as the proof know as again we will see for example. Lastly it is naturally the force is maximum in delay by default prime time will use the clock relationship we have talked about to consider the set up and hold factor as well. If you want to override it you can use last day on the delay command again these are quite dangerous you should be very careful before using them. Now let us say there is a regular regi to HP path and by default prime time will use the normal set up and hold capital register to check the timing constraint. But let us say you have some notion that this the path from regi to HP should not take more than some time. You can apply such time of timing constraint that might relate to a from regi to HP. With this if you apply this ideally in this case if this example ideally in this case you should say get pins regi cp to get pins regi d this is the accurate case more accurate command. With this timing exception pt with node view clock relationship and it will by default it will check whether the delay between these two registers that is the that exceeds the delay between the total path delay minus the set up requirement of the endpoint does not exceed 12 time limit. It will not use the clock edges to show you the timing report it will the timing report will look a bit different. You can also use the min delay command set match delay and set min delay are the most famous example the most famous usage is when you want to constraint a whole combination path from input to output. You can use set match delay or you can use virtual path we have seen this example in the same case. Last timing exception in the multi cycle path we have already discussed that multi cycle path is used to constrain a timing path which it is expected will not capture in single cycle. So let us say you have from ff4 to ff5 the logic is slow you know that so by default set up capture is single cycle hold capture is video cycle and you know that path between ff4 and ff5 is not going to meet a single cycle. So, you can tell sometime accordingly how do you do that like this you tell sometime that set multi cycle path minus set f2 from ff4 to ff5 what it means the default values for set up as I talked before is 1 you are making it 2. Default what is good the case would be that this launch edge the capture would happen here, but now you are telling time time to shift the capture edge by 1 minus 2 means default is 1 2 means you shift the capture edge by 1. So, now the to the capture becomes 2 clock period. If you give set up 5 it will the default is this one it will jump by 4 right. So, let us formula set up set multi cycle path minus set up n means that you first check what is default and then you jump by n minus 1. So, in other words you can also say that the number here tells how many clock periods the path will take. So, here it will take 2 clock periods instead of 1. Now the principle is we have also seen earlier this right back hold edges are determined by set up edges. Now in this case what we did we shift the set up edge right earlier the capture edge was this the call capture edge was this we have shifted it correspondingly hold will also shift if you give just this simple this command what time time will do earlier it was setting hold between this and this. Now it will shift the hold edge at them hold is always set up minus 1 right by default. So, now the hold will get checked between this edge and this edge which is not what we want the hold relationship should remain intact why because if you see there is nothing happening to hold we still want to make sure that whatever gets launched on a particular clock period at FF4 should mean on the same edge it should mean hold at FF5 hold we will still the set up set up becomes to hold becomes small we do not want that we want the hold to be pulled back to 0 how do we do that like this. Actually for any multi cycle path you should give a hold path at them. So, by default ok after applying this command set up becomes this hold becomes this. So, we have applied this command in addition we also applied this. So, almost always the case will be set multi cycle path minus set up end along with this you also tell set multi cycle path minus hold and minus hold this one means you pull back by 1. The fault was this as soon as you give the first command prime time shifted the hold S to 1 by giving set multi cycle path minus hold 1 you are pulling it back you are pulling it back right. So, again remember for set up if you give number n for hold you give n minus 1 right. So, this is multi cycle path. Now let us do an exercise in this exercise there is one case where you can use multiple you can use more than one type of command what is most suitable let us see. Now let us say there is a adder and there is there are muxes A or A and B C and D. So, select between S select between A and B same select between select between C and D same select between select between it depends whether the output goes to E or F. Let us see assume that there are blocks here and each of A B C and D there are blocks and again E is captured and F is captured as a block. Now let us consider case where S is 0 when S is 0 A will go ahead A will go ahead C will go ahead S being 0 F is 0 and A plus C will go to B when S. So, I will write it so, yeah. So, the path the valid path is from A to E A to C C to E A to E and C to E other case D to F D to F. So, if you do not do anything if I am not doing anything if I am not applying any timing if I am not applying any exception what PT does it will report all you can actually it is very easy to make this write it into a law you can you should write this into a law and you do not need to actually improve the process you can simply write the law and define virtual clocks at A B C and D. In fact, let me do this in the in one of the last I will do this in one of the last I will make that kind of perfect. So, by default prime time will report from A to F also because it does not it considers S to be it is a static timing analysis you cannot assume any value in it. Now how do I switch off the path from A to F for example because A to F is not on first case I can use a case analysis I can say set a set case analysis 0 on S. As soon as I do this the only path reported will be from A to E and C to E, but all other path will be switched off D to F and D to F also switched off. Now I also want to check paths from D to F and D to F what do I do now I set the case analysis to S is equal to 1 this is one method of doing it as a good method of doing it. So, you first if you do not want unwanted paths you could first check for S is equal to 0 secondly you should take S is equal to 1 it is a good method, but it is not the best method why because anytime you change the case analysis it will force you to do it delay the name. Because any case analysis needs to be propagated to for example setting case analysis there prime time needs to know understanding consistency of this marks this AND gate it will start doing delay calculation again. And for a full chip the delay calculation there is a command for update timing where we tell time time ok now you can calculate this is a suppressed command update time when we say update timing prime time will recalculate the delays if any of the such constraints right. A case analysis means that the delay needs to be calculated again. For a full chip for a huge design this is a very time consuming effect I mean it can take up to 2 3 4 5 6 hours even 10 hours even 12 hours even a whole day for a big design you do not want that. So, you should choose exceptions carefully other case what I can do I can use a false path I can say set false path path from A to F from C to F from B to E from B to E. Now this is a much more intelligent timing exception why because now after applying the false path in the same session right and able to see timing from A to E C to E B to F and G to F and able to see all the valid timing path this is better than case analysis right. So, in this case we saw that you can apply a case analysis you can apply false path you can even apply a disabled time let us not go into that I mean the worst method of doing this. So, in such in this case there are 2 good methods false path and case analysis and of course, case analysis is inferior to false path because you need to change the value and that will trigger you need to do delay calculation. There is still one more better way of using virtual clocks I will explore that in the lab right how to use the virtual clock that is the best way of doing. So, again a note that if you have got if you apply false path it will be from you need to have 1 false path from A to F second from C to F third from B to E fourth from B to E you need 4 false path some things right. So, we will see in the lab how a virtual clock can be very useful in this case this is where STA becomes such an interesting thing that you have so many commands that are disposed and you should use timing exception you can use intelligent user virtual clock to do the STA that is less computing intensive and it covers all the all the modes it covers like functional mode test mode and it is very effective right. So, 2 engineers can do STA in very 2 different ways right one will be one and one of them will be more sophisticated than the other right. So, that is where STA becomes a good engineering challenge right let us move on let us look at the last slide for the session which is about clock only if we see we saw that it will have multiple clocks you should accurately define clock relationship using false path for example you can tell time time what but how the clocks are related to each other are their asynchronous or they are few if they are synchronous you do not need to do 2 items to define the clock if 2 of the clocks are asynchronous you should set false path now better than there is one more command which is slightly better which is better than false path in some aspects in when you are not talking about noise issues or cross talk issues also so this command is called set clock group and so set clock group and set false path are exactly same when you ignore signal integration we will talk about signal integration later in one of the session but just remember it for now that false path and clock group are much more in the same when it comes to when you ignore signal integrity when you are not worried about signal integrity in one but when you are worried about signal integrity at once do not use false path to define clock relationships use set clock group this is what time time recommends and then we will see why so let us first look at set clock group and then later when we talk about signal integrity we will see why it should be used the set clock group command why it is more possible so first case there is a first case where you have 2 clocks and please remember if you have clocks like this clock 2 and clock 1 where clock 2 is generated from clock 2 is generated from clock 1 more or less most probably they are synchronous if you are generating a clock from a divider more in all probability clock 2 and clock 1 should be synchronous to each other unless an entity is designed it should be accessible right so please be careful if you want to set false path between a generated clock and it is not usually it is very dangerous so in this case you will not have any false path no clock group command simple case second case where clock 1 and clock 2 are asynchronous to each other where any 2 clocks that are coming from different PLS or different oscillators should be false path always if you have different PLS even if the frequency is same these clocks should not be synchronous because each PLS is different to each other right each PLS will have its own lock period each PLS will have its own disrespect you cannot have 2 clock synchronous that are coming from different PLS does not matter what the frequency is right so in this case one is coming from oscillator one is coming from some other source obviously they are asynchronous you can use set false path obviously but when you use set clock groups you can say set clock groups minus asynchronous clock 1 and clock 2 so there is the group command tells that CK1 is a different group CK2 is a different group so you can you are telling that the group to which CK1 belongs to the group to which CK2 belongs are waiting for an interval right. Third case where you have CLK1 and so this is the case where there is a box at one time only one clock can be active so in this case you can tell again you can have false path here clock clock to clock to clock to clock to clock to clock on false path or you can have case analysis here but in this case set clock groups is more powerful you tell it that these 2 groups are logically exclusive that means that in one analysis at one point of time only one clock is active by logically exclusive so asynchronous means both the clocks are active in the design but this path between those are false logically exclusive means that only one will be active at one point of time now from a timing analysis point of view this command asynchronous you can also use asynchronous here in this case for the third case here where there is a mask you can even use asynchronous or you can use false path but logically exclusive is useful when you have single entity when you are including single entity in your analysis you are including noise analysis you see again why why is it important to make sure that you are using the correct switch whether it will logically exclusive or asynchronous when it comes to single entity without signal integrity there is no difference between second case and false case in second case also the clocks are asynchronous in third case also so in both the second and the third case there time time will not check for any path that is launched from clock one and captured it all the other way otherwise right so this is the last slide it was a bit more technical this session we learned a lot more about clock so my promise is that if you understand this lecture perfectly you will be a good SC engineer this session contains one of the most important concepts of SC and that is the clocks and the clock relationships plus timing exceptions timing exceptions so now after understanding this you can define any complex clock any complex related clock you can define the clock relationships now easily and plus you can use the powerful timing exception to make your make your timing analysis much more accurate now the exceptions are very very useful they are dangerous but they are very very useful in a particular chip there are millions of timing path and without having exceptions with so many clocks in place you will have thousands and thousands of paths that are in the faults or they do not matter and and so on right so for example if you if you have like 10 clocks and you forgot to specify the clock relationship you will have so many paths between so all the pairs of clock that might not be even true right so that that is where the timing exception are useful they are a necessary evil why I say evil because any fault timing exception may cause a silicon failure that is why I call them evil so they are evil necessary evil you should use them very carefully and you should reduce them again before sign off if you are working in in the in the industry and you can use them to make your timing analysis much more accurate and much more sophisticated right in the next session we will talk about again the second most powerful concept of SCA which is the on chip addition thank you