 Hello, and welcome to this presentation of the STM32 Debug and Trace interface. It covers the debug and trace capabilities offered by STM32 WB devices. The STM32 WB incorporates all the familiar debug capabilities provided by the STM32 family of MCUs. Flash download, breakpoint debugging, register and memory view, and serial wire trace, and adds high bandwidth instruction trace as well as cross-triggering capabilities in multi-core versions of the STM32 H7 family. The debug and trace infrastructure uses the ARM CoreSight standard, well supported by most tool providers. The debug and trace infrastructure is composed of three distinct functional domains. Debug access infrastructure includes the debug port, SWJDP, and access ports, or AP, which allow access by an external debugger to the target's trace and debug features. Cortex-M0 Plus Core includes the processor and associated trace and debug units, DWT, BPU, and CTI. Cortex-M4 Core includes the processor and associated trace and debug units, DWT, FPV, ITM, ETM, TPIU, and CTI. In addition, there are system debug features including cross-trigger matrix, or CTM. Connects the CTIs to allow simultaneous halting of both cores, triggering of trace, etc. DBGMCU provides proprietary features such as freezing of timers during debug. External trigger input-output allows an external signal to trigger debug or trace, or generates a trigger pulse for synchronizing external equipment or components. Note that in STM32WB devices containing the secure root security services, the Cortex-M0 Plus debug unit is disabled. The minimum configuration for debug requires pins PA-13 and PA-14 to be allocated to serial-wire debug. SWDIO and SWCLK respectively. Serial-wire debug uses a special serial code driven by the debugger on the SWDIO or JTMS input. This is recognized by the SWJDP, which switches to SWD mode after reset JTAG mode is configured by default. ST-Link and most third-party debug adapters, for example U-Link, support serial-wire debug. Access Port AP0 allows access to the debug and trace features integrated in the Cortex-M4 processor core via its internal AHB bus as well as to the DBGMCU. Access Port A1 allows access to the debug and trace features integrated in the Cortex-M0 Plus processor core via its internal AHB bus. The single access ports enable dual CPU debugging. All debug-related registers in the Cortex-M0 Plus core are accessed via the dedicated AHB access port AP1. The ROM tables contain pointers to the base addresses of each debug component visible from the access port or AP. They are used by some debug tools to automatically detect the topology of the core site infrastructure in the target. The SCS or System Control Space contains the registers for controlling the processor core while in debug mode. The other units are described in the following slides. Note that there is no support for trace on the Cortex-M0 Plus processor core. All debug-related registers in the Cortex-M4 core are accessed via the dedicated AHB access port AP0. The ROM tables contain pointers to the base addresses of each debug component visible from the access port or AP. They are used by some debug tools to automatically detect the topology of the core site infrastructure in the target. The SCS or System Control Space contains the registers for controlling the processor core while in debug mode. The other units are described in the following slides. A data watch point or DWT comparator compares one of the following with the value held in its DWT comp register. A data address, an instruction address, a data value or the cycle count value for comparator zero only. For address matching, the comparator can use a mask so it can match a range of addresses. On a successful match, the comparator generates one of the following. One or more DWT data trace packets containing one or more of the address of the instruction that caused a data access. An address offset bits 15 to zero of the data access address or the matched data value. A watch point debug event on either the PC value or the access data address. Or a CMP match and event that signals the match outside the DWT unit. The Cortex-M0 processor core has eight comparators allocated to instruction fetch address matching. The Cortex-M4 processor core has six comparators for instruction fetch address matching and two for literal load address matching. In other words, data reads to code space. The latter can only be used for patching. Software can write directly to any of 32 by 32 bit instrumentation trace macro cell or ITM stimulus registers to generate packets. The permission level for each port can be programmed. When software writes to an enabled stimulus port, the ITM combines the identity of the port, the size of the write access, and the data written into a packet that writes it to a FIFO. The ITM outputs packets from the FIFO onto the trace buzz. Reading a stimulus port register returns the status of the stimulus register empty or pending in bit zero. If multiple sources generate packets at the same time, the ITM arbitrates the order in which packets are output. The sources are listed here in descending order of priority. In the STM32H7, the embedded trace macro cell or ETM is configured for instruction trace only. In other words, data accesses are not included in the trace information. The trace port interface or TPIU is only available from STM32WB packages supporting the parallel trace port. The single wire trace port or SWO is available from all STM32WB packages. The trace port width can be programmed from one to four pins. The bandwidth scales proportionally to the number of pins and the trace CLK frequency selectable via a divider in the RCC. By applying filters and triggers to the trace sources, ETM notably, the average amount of trace data can be reduced, allowing a lower clock rate or reduced number of pins. The trace SWO pin is multiplexed with the JTDO signal, which is part of the JTAG interface. Hence, single wire trace is only available when the serial wire debug or SWD interface is enabled. Cross triggering can be used in dual core devices to halt both cores simultaneously. When one core hits a breakpoint, its halted output, indicating it has entered debug mode, propagates to the other core and causes it to enter debug as well. Similarly, both cores can restart simultaneously. The cross trigger feature can also be used to halt the processor with an external trigger signal. This might be an edge on one of the IO pins. There is a cross trigger interface, or CTI, in each of the Cortex-M processors. To use any of the cross trigger features, the CTIs must be programmed accordingly by the debugger. The required trigger input signals, or Trig-IN-N, and trigger output signals, or Trig-OUT-N, need to be connected to the cross trigger matrix, or CT-M. The CT-M comprises up to four channels, allowing four different events to be propagated in parallel. Trigger inputs can be combined in the CTI so that any one of the combined inputs will cause an event on the connected channel. Similarly, a channel can be connected to several trigger outputs, so that one event can trigger multiple actions. The DBGMCU is located on the Cortex-M4 PPB bus and can be accessed by the debugger via the AHB access port AP0. It is also accessible by the Cortex-M4 software. The DBGMCU IDC register provides the device ID and revision codes in STM32 standard format. The information is also available in the debug port, or DP-TARGET ID register, accessible only to an external debugger. Low power mode emulation means that the debugger connection is not lost when entering low power mode. It eliminates the need to replace the low power entry command, for example WFI WFE, by a while loop. On exit, the device is in the same state as if the emulation was not active, apart from any changes made by the debugger during the low power mode emulation. Peripheral clock freeze is particularly useful to prevent a watchdog timeout from resetting the device while debugging, without having to rearm the watchdog with the debugger. It also allows timer values to be inspected and corresponding interrupts to be suspended until normal operation is resumed. The trace CLKEN bit ensures that the trace port output is only clocked when needed. This avoids unnecessary power consumption. On certain packages, the TRG-IN and TRG-OUT pins are not available, only the bidirectional pin is used, and the direction must be chosen using the TRG-OEN bit.