 Hello everyone. Myself, Sanjay Utke, Assistant Professor, Department of Electronics Engineering, Valchand Institute of Technology, Solapur. Today we are going to discuss Conversion of various flip flops. Learning outcome. At the end of this session students will be able to convert various flip flops from SR to JK, JK to D flip flops. Outline. JK flip flops. It's a race around condition. T flip flop. D flip flop. Question and answer. Excitation table. Conversion of SR to JK flip flops. And finally, References. JK flip flop. In earlier discussion we have gone through SR flip flops in which when SNR both are equals to 1 this condition is not allowed. When both are equals to 1 the output is uncertain or it is invalid. So this difficulty is overcome in the JK flip flop. So this is the construction of a JK flip flop logical diagram. In the input stage we will find two NAND gates having three inputs. The first one J input then clock and Q bar. The lower one NAND gate will have three inputs again clock K and Q. So this is the truth table for the JK flip flop. So for we will discuss now various conditions J equals to 0 So at this stage the output Q will remain as previous whereas Q bar will also remain as previous. Now let us go to the truth table. So the first two columns J and K flip flop. The third column is the previous state Q before clock pulse applied. The fourth column is Q after clock pulse applied. This is Q plus 1. And the last column is the comment. Now let us go to this truth table. When both J and K are equals to 0 the first row when previous state is 0 the output the next state will remain same that is 0. In the second row again when J and K equals to 0 and if previous state Q is equals to 1 Qn plus 1 the next state will be equals to 1. That means for J and K equals to 0 there is no change in the output. Now the second combination of inputs when J equals to 1 K equals to 1 for Q equals to 0 if the previous state is Q the next state will become 1 and here again J equals to 1 Q equals to 0 and if the previous state is 1 the next state will remain 1. Third combination when J equals to 0 K equals to 1 if previous state is 0 the next state will be 0 if previous state is 1 the next state now it is going to change that will be equals to 0. So when both J and K equals to 1 and if previous state is 0 the output state will change to 1 please note down output is changing from 0 to 1 and if the previous state is 1 the output will change to 0 it means that if previous state will be 1 if previous state is 1 the next state will be 0 it is nothing but toggling of the output clock pulse. So in the summary when the inputs J and K equals to 0 there is no change in the output if J equals to 1, K equals to 0 Q equals to J Q bar equals to K and if both are equals to 1 the output will toggle between 0 to 1 and 1 to 0 so this is the timing diagram again referring to this truth table I will take one example if J equals to 1, Q equals to 0 it is a output Q will be high that is 1. Now here if J equals to 1 J equals to 1, Q equals to 1 the output will toggle to 0 why? because the earlier it is at logic 1 level there is a round condition this is toggle condition when both J and K equals to 1 the output of the flip-flop will oscillate between 0 and 1 at the end of the clock pulse the value of Q is uncertain so this is a T flip-flop the T flip-flops is obtained by shorting the two inputs J and K equals to 1 so this is basically a J, K flip-flop here J and K are shorted so we will have only one single input as T so the truth table for this will have either 0 or 1 so in T flip-flop if the input T equals to 0, output is 0 if input T equals to 1 it is a race around condition the output will be toggle so this is the truth table for the T flip-flop T equals to 0, output is 0 if T equals to 1 previous state is 0 now next state will change to 1 if the previous state is 1, next state will be 0 that is why the name is given T flip-flop this is a D flip-flop called as delay flip-flop it is obtained by complimenting the J input to the K input of the basic J, K flip-flop so this is the diagram it is basically a J, K flip-flop this D flip-flop is obtained by complimenting taking a compliment of J input and giving it as a K input so in this case we will have only two input combinations as 0, 1 and 1, 0 if D equals to 0, output will be 0 if D equals to 1, output will be 0 which is shown by this truth table etc. what is the difference between T and T flip-flop? in T flip-flop J and K inputs are shorted hence the input is either 0 or it is 1 hence the output is either 0 or toggle between 0 and 1 in T flip-flop the K input is the compliment of the J input the output is equals to J input it means if J is equal to 0, output is 0 if J is equal to 1 this is the excitation table it is a very important part of the flip-flop conversion in electronic design and excitation table shows the minimum inputs that are necessary to generate a particular state when the current state is known they are similar to the truth table and the state table but they rearrange the data so that the current state and the next state are next state to each other on the left-hand side of the table and the inputs needed to make that state change happen are shown on the right side of the table so this is the excitation table for SR flip-flop present state 2nd column T plus 1 next state so these are the output state present state next state and from this we have to determine what should be the inputs of the SR flip-flop for 0, 0, output 0 to 0, output we must have 0 and X X is the don't care condition so it means that if the next state is 0 and if we want the next state to be 0 the input combination SR will be 0, 0 and 0, 1 so in similar manner these are the different input combinations for the different outputs expected this one is SR this one is T, JK and T flip-flop conversion of flip-flop conversion of one type to another can be done by using a combination logic circuit if a JK flip-flop is necessary the inputs are given to the combination circuit and the output of the combination circuit is given to the input of the actual flip-flop therefore the output of the actual flip-flop is the output of the required flip-flop we need to combine the excitation table of both flip-flops and make a truth table of flip-flop data input and queue as the inputs and inputs of G1 flip-flop as the output then follow the conventional method of logic design it means conventional logic design means we have to determine using a K map we have to find out the boolean relation between the input and the output so this is what conversion of flip-flop using a logical diagram so this is the given flip-flop for example this is a suppose we want to go for SR to JK flip-flop so SR flip-flop will come over here and this is the combination flip-flop a required flip-flop so the required flip-flop is JK flip-flop so the inputs will be treated over here are J and K and this is the given flip-flop SR so this is input S and this is input R so if you look at this carefully the inputs conventional circuit will have the input external input as well as the inputs from the given flip-flop this is the conversion of SR to JK flip-flop okay so this is the conversion table that makes use of the excitation table and the truth table on the left hand side you will find the JK flip-flop table and the right hand side SR flip-flop because SR is the actual flip-flop we are using using SR flip-flop we are deriving a JK flip-flop so make a note of this JK flip-flop we will find which is required flip-flop we will find at the left hand side whereas SR flip-flop S truth table excitation table you will find on the right hand side so JK flip-flop 00 for this input condition we want the output to change from 0 to 0 what are the inputs? the required inputs will be 0x that is 0 1 1 0 similarly again for JK equals to 0 if the present state is 1 if I want the next state to be 1 what is the SR input? it is x0 so again the second and third and the fourth column JK inputs are 0 1 0 1 I want present and next state at 0 0 then 1 0 what are the inputs? 0x and 0 1 again the last last two rows 1 1 and 1 1 so SR next states will be 0 1 1 0 what are the expected? inputs SR 1 0 and 0 1 so this is the K map gives the regular conventional method to find out the S input this K map consists of J 0 1 and K Q N here also so with this conventional method we got the S is equal to J bar Q N whereas R is equal to K Q P so this is the conventional method we are using these are the references for the conversion for the various flip flops thank you