 So, in the last, in the first session of design compiler map, we saw how to get the libraries. We read in an example RTL file for the collaboration report, we studied how we look it to how to report from the library. So today, we will go ahead and compile a design. This design consists of about 8 to 10 files of telegraph. It is a decent enough design to do the experiment. It is even contained in the library. It looks, it is, I am not very familiar with the design. It comes from Synopsys. It also has some power controller. So, let us look into the design first a bit. And then we will read in this design. And we will set the constraint in the normal condition. And then we will go ahead and compile the design. Now, as a synthesis and timing engineer, it is not necessary that you know complete inside and out of the design. Even without knowing what actually is implemented in there, as an engineer, you could always synthesize the design. So, the major things to know are first of all the of the nine conditions. And in most of the cases, the synthesis engineer will help with the design. We will decide on that. Plus, obviously we should know about the, some interface, something about the interface to which the block being synthesized connects to, so that we could work, see input out to the data. Obviously, we should know what are the blocks, what are blocks are there in the design, what are the sequences and what are the languages. So, just by knowing a few things, we could do the synthesis and then later do lot of analysis and reporting to make sure that the synthesis is correct. So, it is not at all necessary to know each and every part of the design. Since I do not know each and every part of the design, still we will synthesize it and still we will get some very useful data out of it. So, these are the, all the .v files listed on the desktop. This all constitutes the design. The top level is top odc.v and the module name is Chiptop. So, we could see there is a mem write burst, mem write valid, there is a clock, the reset signal, there is a power signal. So, it looks like some kind of a memory controller kind of a design. Which just by the name it suggests that it is some kind of a memory accessing with some kind of power, some functionality to limit the power. So, we see the inputs and the outputs. Let us see what are the instantiations here. So, we see that. So, it will the top level in most of the cases will be a more or less a structural design. So, we see there is an excellent decoder. We see there is some pairs and terminal purpose list. Then there is a multiplier, there is a signed multiplier. So, it is good that you have a multiplier, you have a data pathway. We have a power controller, there is some address generation logic and there is a memory mem x hierarchy. Now, this would be better. So, there are two instances of there is one mem x hierarchy, there is mem y hierarchy and I guess these mem x and mem y higher blocks contain the actual memory instantiations. We could see that let us graph for three what where is the memory instantiations. So, yeah. So, memory instantiated in the block mem x. So, this is the block. Now, see the interesting thing about this block is that it has some instantiations of buffers. So, now the RTL designer for some reason chose to instantiate some buffer in this RTL. Now, in this case this RTL now is not not independent. Why? Because this is using some buffers from a particular format level. If I want to use this RTL with some other sign of the library from some other provider, I will have to make sure that these buffers get released. So, in most cases in many cases many cases we want some specific buffers to be in place. So, we will instantiate them explicitly inside do not touch on them. So, that if we does not remove it to reduce area. So, there are various reasons why it is done sometimes for layout representation. There can be many reasons. So, but we see that there are a lot of buffers here and I guess they will be set to do not touch later in the future flow and the number of buffer buffers. So, address looks like all the inputs are being buffered and also have been buffered. So, let us see this input common address. So, we see that yes the common address is being buffered. So, this common address in which will be via driven by the buffer goes through memory. So, it is a very good practice to buffer the inputs to memory and the outputs to memory. Usually what happens that memory is we have to make sure that the transmission through the inputs of the memory from the output of the memory are very good. So, it is a good practice to have explicit buffers and tell the layout engineer that please make sure that these buffers are please close to the memory marker. So, that way you are making sure that the transmission numbers are good. Usually memory is like this. So, this looks like a one port read write memory. So, this is a usually the memory is like this have high end systems and very critical and always scientific in the memory. Either to the input side the set up and hold windows of the output are being strict and we have to sign from the clock to the out state out and we will need more compared to clip clock to complete the process. So, it is always good to maintain good transmission numbers at the input from the output. So, now we see that there are two instantiation from the memory. Now, if you look at the RTL there is no module definition for this memory. So, how does DC know about this? So, DC needs to know the module definition for each and every block right each and every instance. It needs to know what is the module definition. Now, for this memory the module definition does not come from the RTL. Then it is not a synthesizable logic. It is a macro that is already being that is already constructed and given to you to be used directly to be used explicitly. That is why we have a tortless problem. So, yesterday we saw that there is a memory tortless. So, we see that we have a memory tortless of SRAM. This is this and in our let us go to the work area and we will already started design compiler. So, now we have to make sure that this memory is got to be the part of the link library not the target library. So, what we will do now is we will read in the complete RTL and see what happens. So, I will copy paste some commands. This way you can actually go ahead and make your own script files with the good practice. Whenever you synthesize the block to make a script file. So, that you can just source it inside the different when you want to repeat the process you do not have to write each and every command every time. So, I have a script file I will just copy and paste up from this. So, we will just review these steps. I will set the search path, the link library, the target library and the defined designer before sourcing the RTL. So, I have set the search path, the link library and the target library please note the link library contains the SRAM path to the target library only points to the client. Now, we will read in the complete design. So, now you could use again I would respond using the analyze command. So, you can say I have a list of found. Now, this list of files since it is very long it can be it not necessarily be in the order of in the DC will it is any red lock to be able to read out the for the red lock file. So, it should not be a big problem. Let us read in this red lock. So, now this is just the analyze step and it searches for the RTL models in the search path. So, it searches in RTL. It finds all these files in the RTL and it will read. So, there is no syntax error otherwise you will have syntax error you will see errors. And as soon as it reads in the RTL it also loads the dv files the target library on the link library. Now, we will elaborate Chiptop is the module name of the top level design of Chiptop. We will elaborate we want to elaborate it. Let us do that. Yesterday we read in one file. Now we have read about 8 to 10 files. So, it will start the elaboration process. So, the elaboration process will map. It will start inferring hardware and map it to the GTEC components. It will tell you what are memory moments are there what are Chiptops are there. Yesterday we saw the inference for one of the blocks. Now, let us see the inference for the case analysis. So, we see that so this law it is very it is a good practice to review this law very carefully. So, we have learned how to how to interpret this. Now, let us see one of the files where there is a case statement. So, it tells that there is a case statement at 949 in this file. And it interprets yeah let us open this file. So, there is a case statement here. And now so there is a function and there is a case statement. And it determine so this function select 15 it will be used somewhere. Yeah it is used to select something for function implemented. And this it tells us DC reports tells us that this case statement is both full and parallel. You could see that so this election is a hex the cells is a hex number and all the 16 possibilities are existed. And only since only one can be true at a time it is both full and parallel. So, let us see the report again. So, it tells us that in gpr.v yeah there is a case statement in gpr.v it is full and parallel automatically. We have no synopsis super case or parallel case pragma view. So, it is so if the pragma view it is a user class something it can give a user keyword. So, that it tells you that you as a user are forcing to consider the case statement as either full or parallel. If it is not there it is a synopsis. It is very it should be very careful in your case statements you could make sure that they are either auto or user preferably they should be auto. Second circumstances if you cannot make it auto or if you know that yes only one possibility connected at one time and I do not need to write an empty code you could give a synopsis pragma full case or parallel case and here it is a user. If it does not recognize the case statement as full and parallel you should very carefully review your code and make sure that this is what you understand. Otherwise either there will be latches or there will be priority encoder a slow logic. So, I would recommend each and every one of you to whatever RTL you read you just very very carefully you should review this elaborator code. So, one thing you could still do is you can elaborate and what I will do is let me remove. So, if you want to remove the design you could do a remove design minus or minus let us see remove design. So, the help says that you could remove the designs and you could also remove the design and library too. So, you do not want to remove the libraries let the libraries be loaded in you do not worry about that you just want to remove the design. So, I say remove design minus design it will remove all the design that is read. I will read in the design again I will elaborate the design but this time what I will do I will want to store the log file into some time. So, I can use the output realization same as the next one into a lab dot log and now I see that what a lab dot log comes in. So, it contains it is a very good practice to have separate log files for important norms like elaborate like compile or you want to report timing. So, it is good to create to store this output into a file so that you could review it at that time or at a later stage. So, it is a log of the quality of the file. So, you could review it in a separate file and yeah. So, it also gives the display outputs which is kind of boundary hypothesis. So, dollar display, dollar time, etc. are simulation constructs they are used in the RDF so, but DC goes on. Okay, it just gives the output but it does not affect any synthesis it does not affect the quality of the file. So, you have to make sure that when you write code then you could try and see that you should only use the synthesizer code. If you want to use non-synthesizer constructs like dollar display and dollar time you could do that but using some some matters like your depth to make sure that they are not write doing it is a good practice. So, yeah. So, once you have reviewed the reviewed the log file of elaborate you can go and now you are ready to set the environment condition set the design constraints before proceeding to compile. Now, can I do anything more can I do any more checking yes I can do a lot of checking I can do a lot of reporting and this thing let us see one important checking command for check design let us see the help the check design will give a summary of any warnings related to input port in my type not connected output port not connected multiple doesn't some of these warnings are you can ignore depending on the case some of these warnings are more serious so, what we could do is let us run a check design minus summary first see what is the summary of so, when we run check design summary it starts growing a summary of problems that DC found in the design these type of checks are called lint check static so lint lint checks are static checks run on the port to find out problems that might affect your synthesis. so, the check design is a basic is a very basic tool from design compiler that gives you a summary of results a much more sophisticated tool is this file from you will encounter that in your course maybe in some other course or in the industry so, it is a very famous tool that gives you the power of writing your article for problems even before going because in many cases please for bit checks synthesis is a very time consuming and you would like to know these problems that exist before even going to synthesis it saves a lot of time so, let us see the warnings so, it tells us that there are a few next with no load there is one multi driver which I think is a serious problem that should be corrected so, ideally for cases like multiple driver or for tri-state drivers ideally you should instantiate those the cells directly you should not let DC map any tri-state logic to a tri-state logic it is a good practice not to have any tri-state logic as part of the article it complicates things later in timing analysis it is a good practice if you want tri-state you should use it explicitly in your article not let DC map it tells that so, it also tells that what so, it tells that in instruction decoder there are 8 codes what are they some of these problems might be there are many times a designer chooses to leave some codes open or to leave some input code under them so, that we can add design to it later so, these are not big problem multi-driven is a big problem might be a big problem later on so, it gives different a kind of warning so, each warning has a group it has a code number for example let us see this length 30 is a group of so, all these warnings have a length 30 code you could actually check what length 30 means by doing a man on it so, this tells us that this is a terse version of a check design warning message so, length 30 is a code that is used for warning messages reported by similarly, all the warning in a messages inside DC will have some code you could do a man on that code to know more about what it means so, this is a very generate it does not tell much very generate a warning message now, if you do check design minus without some option it will start throwing up the start now telling earlier it was telling the summary now, it will start throwing up what exactly the problem so, it is telling me that in this design a pin on this module is connected with the logic 0 or logic 1 this is not necessarily a problem and it so, it is not very easy to remove all the warnings from them so, you could look out for specific cases for example what I do here is I will again I redirect the output of this check design into a law and then I will open this law and I will search for multiple drivers we see that in this log file there is a non summary of them it also gives a group of commands which is linked to which means no load and yeah so, this is the warning which I am looking for the same net is connected to more than one pin on some of these these type of problems you should look out for is that when same net is connected to more than one pin to make sure that your design is correct and and it goes back to the distribution with three water options there are specific options like it also tells you whether you have multiple designs so, it also tells you that see you could also get this kind of information where you have multiple extensions so, we discussed in one of the lectures that how do we resolve multiple instances we see that as part of the compile we will use a unified process so, it tells us that design is 13 times so, you so, it is good thing to run check timing, check design and go through the important important it give whether it gives an interest or warning go through them correct them as the case may be and then proceed so, now we write in the design we did a check design and you could read more about check design so, there is a man page again which it gives you and it tells you detail what each and every option means right there is also a case of no warning you could do that the first check so, you could prioritize this by making sure you list the errors first now there are no errors so, so, you could it is a very powerful command now, we start working on the environment conditions so, if we go back to the lecture that this is environment conditions there are majorly three kind of the environment conditions we have to define first thing you have to make sure that operating conditions are different so, let us see what are the commands are there to specify or report operating conditions so, there is a let us see what operating condition is in place so, now so, we see that we want to see what are the conditions are available in the library obviously, we will use this transactional library for this so, we see that there is an operating condition something is part of this library and we want to set this operating condition there will be also an operating condition defined in the library library now, in this case both of them are different this is a point this is 125 c this is 25 c this is 1.2 mode this is 0.95 mode this is dangerous as I mentioned in the last lab session I do not have the worst case library for SRAM I am using both these people are doing but in a real design in a real industry scenario this should not be the case you should always do the worst case for all these cells that are in your design whether it be memory or anus macro and make sure that the operating conditions are same for each of them and voltage is same otherwise it will give you problem otherwise it will not be active so, now I want to set the operating condition set the operating condition if you help on this so, there is operating condition so, I have come on here so, you could always lead in the min library also the part library also you could set the condition so, but it is not needed for sensitive you are going for some low amount so, what I do I just since I have just read the math library I will just use the math condition so, we can say now and we use the operating condition in this one so, now it tells we have set the operating condition it searches when we say this it searches for this operating condition in the min library it found the operating condition here the operating condition is set now this operating condition tells we see what is the temperature what is the process corner what is the voltage but since we only have the bursted library loaded so, anyway that library itself corresponds to bursted operating condition now, the second thing what we want to do is we want to set the load at the output and some function or driver cell in the so, now we want to set the load at the output so, I will we will see one of few reporting command is the very useful so, to see all the inputs in the design we can type one inputs and it tells it gives me a list of inputs that are available to us since memory burst is the burst type input so, it gives the split in terms of the number of bits clock we said we can similarly here we have all outputs this gives the list of all the outputs available to us right so you could use those these things now, we want to set the load now, I as in since this we do not know what load to set but I can also estimate nobody has told me designer does not designer is not told what load to set but as an engineer I should be able to work it out how what I will do is I will now search the library and see what all buffers are there so, I will try and get a list of buffer and see and make sure that the outputs of my design are able to drive a load that can be driven by the buffer of the maximum size not if not maximum then very near to maximum let us see let us first see the list of buffers in the design so, we saw report list what else what else are available so, buffers will be starting this one is not there so, we saw so, there is a piece of n bus so, we have n bus 2 n bus 4 n bus 8 n bus 16 n bus 13 so, by experience I could say that okay x 16 or x 8 price should be good more so, this is where experience comes in x 32 is a bit large so, what I will do I will open up the library models I should open up the worst case what I am looking for I will search for this buffer 16 buffer and I will see at the output what is the max cap so, so max cap is 16 so, now if I want that my design output drive should be x 16 then I should be able to drive this load this load so, this if you see even in the look up tables whether it is power or timing it is a timing look up table the index to corresponds to the cap the max cap is 16 that means an x 16 buffer can drive up to the 16 pf of load now do I want my output load to be this I am assuming that it is driving I am assuming in x 16 cap on my output so, I can easily do that I can say that set load let us see what set load tells us so, set load tells us there is a min there is a min there is a max you could read more about it what is subtract fill load it adjusts for the pin capacitance from the value and so on minus fill load or minus value load so, now so, it also tells us that you can set load on either a list of nets or poles in this case we are talking about poles so, we would say set load of let us say 16 and we want to set this load up on output right so, this is the way where I can set load right now the the second thing we want to do is we want to set some so, this is telling DC this is if you do not set the load and function of the input you are working in a very idealistic world so, it is always a good practice to estimate the value of the load and function load at the output and function at the input so, that your synthesis becomes more accurate so, now let us let us set some function value of the input now what function is set now output we assume a maximum driving capability input we will assume the worst case we should always assume the worst case we will assume that a very weak driver is driving the inputs so, let us assume an excellent driver is driving the inputs now let us see what is the maximum transition again we will open at the library we will go to let us say we search for n buff this is n buff x 16 we search for n buff x 1 now let us see what is the is there any max transition at the input max transition will come at the input max capacitance is usually is there for the output there is a max transition of 1.024 I think when we look at the output timing window output timing lookup table let us go here we see that 1.024 we need the max so now one again the now I know that the transition of 1.024 1.024 is very very long now we will see that we will apply a clock of 2 nanoseconds so we will synthesize the design at 500mg now when the clock itself is 500mg our 1 nanosecond transition will come so we will look for some realistic value so now from experience I know that let us look at buff x 2 so a buff x 1 is very let us look at what happens in case of buff x 2 so let us look at what is the max transition here so again max transition is so now what what I should do is we have some kind of guidelines so what the guidelines we follow is that industry is that called technology like 90 for 65 and beyond if I 45 or 28 even we will limit the max transition numbers to somewhere around 250 300 please a transition of more than 100 is very very bad and you believe in most of the cases you go to so what we could do is again we can say that let us put our input transition to be let us say 500 px to be given you could always change the solulator 500 px itself is very very efficient so there is a command called set input transition let pb help again it again tells whether it is the rise function, fall, you know max so again the argument it except the list of input codes now we should be careful of excluding the clock on the list of input codes we should not set any input transition so how do we do that so if we do not specify any rise or fall it will assume the same function for both of them we do something like this so a list of if we say all inputs it will give me a list of all inputs if I say get course clock it will give me a clock what I need to do is all inputs and get course both return an array which is called a collection so I need to just subtract this from this the command is for remove from collection from the collection all inputs I will go ahead and remove the clock what it gives me is again a list but with clock code option now I will use this kind of structure this kind of coding to set input transition I say input transition could be since the time scale is nanosecond 300bs means point 3 point 3 on so a square brace means you are executing a function so I want to execute this function now I set the input function now you set the operating condition you set the output load do not worry if you are not able if you are confused about how to choose the values of input function output load experience will help you as when you start working on it you start seeing the value what is bad what is good so then what we do is we set the pilot model so let us see again I am trying to work like a layman assuming I do not know what is the command to set and report pilot model I can always use help now there are so many you can go step further and do a by load so there is something called report by load let us see if there is any by load loaded here so so it reports by load call this library which we saw earlier as part of report list so as soon as we did a report by load since there is an already there is a by load automatic by load selection available in this library in the sense that for each module it will apply some by load model based on the area how does it know the area it does not know the area as of now there is some using some logic it is it is just applying some by load which is for QA on all the designs most of the designs you could choose one of the by load model so let us choose since I do not know it is always an iterative process the first time you do synthesis you will have some area numbers in place and you will have the idea but since I am synthesizing it for the first time I do not have any area number with me there are so many so it reported so it tells me that it goes to by load models for QA location checked up and then for memex it chose this one because I guess for memory it has the area number because the memory is a macro it has a dot list and it has some area I will show you let us open the memory list and let us go to the area as so okay so this memory library again has by load model this is not normal usually all of macros and memory list will not have area so it has some area which is about 119 K microns it has this area so based on some distance it has some again numbers available it chose one of the now I do not want this by load model so I can set my own set by load model so this is the set by load command or set by load mode command so let us start with something sometimes so now the single command for set by load it will set all the things we say mode we say let us choose stop let us choose the reverse case let us choose the mode name let us choose mode top then let us choose the library so we set by load and now we could change we could select the model name so let us okay let us choose this let us choose 28000 it tells for the complete design if I want to do that and let us do it on current design this command is obsolete so we have to use this command is obsolete set by load model now it has split so we set by load model minus the library name name is optional so let us leave it leave it this command set by load model minus name now let us report the by load model what does it say so it tells us that the design trip top has this by load model set now for design instruction decoder it is choosing for QF just because I guess since it might have some services instantiated let us set the by load model by load mode also so top so now to this area so this area number this comes from the by load let us look at the again let us look at the lid let us look at the by load so we set this one this is the area number and it is low open gap and the distance value comes from here now the by load is set so usually in the lower technologies you do not have this kind of area based by load usually it is a custom by load that is each design you have some by load and you apply that by load so that depends on what kind of technology that you are using you can always do some experiment so let us look at the good by load model or a bad by load model because you will only know after the design goes to layout so if your estimated number if your estimated net delays when you go to layout if they blow up a lot that means your December is gone but if the timing remains good even after the layout if the timing of the post layout is very similar to the pre layout very similar to the estimated value you selected a good by load model now as technology goes on thinking the by load model does not provide a good estimate so we have other methodologies that are replacing by load model and I will discuss that some of those in other lectures upcoming lectures but do not worry too much about which by load model to select you could always start with some value now we will be chosen by load model operating conditions now let us also look at a command for report port so report port will tell you what will you actually do so it tells us that the port input the fill load is 0 the by load is 0 we set the tapestance for so we set for the output for we have set the load to be 16 I guess there is also a command for the port for the port so there is a report port minus per post per post means it will give more detail the series now it is also started to give us something so whatever we set with respect to port is available to us in report port command for example we have set the function to be pointing so here it is reporting that each of these input ports have a base function so you could use this command to verify whatever you have applied being applied correctly now we have to set the design constraints before going to compile so design constraints first things first we have to specify the clock how do we specify clock we use the weight clock command so we know that the port is called we saw that there is a port called there is a port called clock we create a clock on this so create clock minus name clock so this name can be anything we are creating a 500 megahertz clock on the post clock so the clock name and the port name they are both same please note the distinction between this is port name which is sprinkle port of the design this is a name just a name so I do this so the clock is created one means that this is successful you could also do a report clock and see what our clocks are making in the design so this is the clock waveform means that at 0 there is a rise edge so if you do not specify anything so create clock has not many options if you do not specify any waveform value any waveform list then d3 will assume that it is 50% so 0 writes one call total period of 2 500 megahertz we created the clock now we have to create some input delay and output delay let's take some value typically for such a fast clock 500 megahertz clock input is the clock equal piece to nf let's say I will have 1 nf out of this to all the inputs so I give 1 nf input delay how do I give I set input use set input delay I do minus it so there are so many options I will do the most standard thing I will say with respect to what clock with respect to the clock clock nf is clock I give a value of I give a value of 1 1 nf please note a set input delay without minus clock option it will work with representation so you have to make sure that always you give a little clock for set input delay in this design we only have one clock so we will define with respect to this there is a conceptual version clock which I discussed earlier we will see lot of lot more of clock in unit type and I do this on all the inputs except wrong so the clock input since the clock is coming there does not need an input delay so again I will use this construct remove from collection and from list of all inputs I will remove so set input delay is done again I will do the same value for output delay and giving 1 nf to the output this is very simple again we choose 1 nf the reference clock and we choose to do this on all the outputs this is the very basic of the design constraint that we applied we specified the clock we specified the input delay and output delay now you are ready for this if your design contains multiple clock you have to define all those clock you will see the case we will probably see one of the examples where you have because then the clock relationship becomes also important here that does not make a difference because there is only single clock in a multiple clock design it may happen that few of the inputs work on one of the clock domain so we include output delay commands with this type of thing you have to choose the correct clock so this now we have defined now we are ready for this again we will do a report forth minus verbose and see that this is the the key there will be a field where so it tells us that there is an input delay defined on input forth this so we saw the input delay there would also be an output delay table so there is a constant table so output delay input delay have option of rise called max and min for synthesis usually you will always be worried about the max value so if you do not specify anything it will assume the same value for both ridin for max and min so you could change the values for if the input is binding so there is lot of configurability but for for synthesis this is not very important we are only worried about we want to reserve some time we want to give some time to the outside load on inputs and outputs so we specify the input delay without the item for that it is enough for synthesis for synthesis the max value is important we are talking about the worst but the min value becomes very very important for starting time so when you talk about synthesis all the values we gave the input delay the output delay we choose the worst case parameter all worst case stuff since we are worried about the performance but when we go to unit 5 and we learn study unit 5 we start a time analysis the min delay become also become important we also start doing the math so all these commands which are simple in DC 2nd input delay the top rating condition now we will become lot more complex and we will come to the time we will come to the start time analysis so this forms the synthesis these are called timing constraints creating clause simple delay, load to delay they are simpler for synthesis but they might become lot more complex for starting time analysis see that in mind now we have everything defined so what we are going to do I will just now see what all options the compiler give so there are two commands compile and compiler since compiler is available to us I will start using that compiler is much more sophisticated than compiler so let us see what all options should I give in compiler to start with to start I want to do a simple compiler without plan and without log rating later so to start with I want to do a simple compiler so what I will do is I will choose the simple options no boundary optimization we will come to this I choose no sequential output inversion these are all sophisticated techniques but I do not want to do any of that so I just use simple things since scan if I give scan it will do scan it will do minus scan it will assume it is a non scan thing so no is a negative option so I do not want any boundary optimization I do not want any sequential output inversion and I do not want any other stuff so I can do this however I can say no design rule to not fix design rule in this class but I will or I can choose only design rule to fix only design rule whatever I can do that but this will be the most simplest of the command compile as per minus no boundary optimization no sequential output inversion so this will synthesize the design without scan without log rating in place it will not enable boundary optimization and we will read more about this no sequential output inversion so I will express enter and now it will start combining the design let us see the messages so it loaded it loaded stuff it loaded some loaded the design by component it loaded the now it starts it is undoping some hierarchy before pass one I need ideas fine so now it will do a pass one it has again it will do multiple iterations so now it gives the last time now you see it is working on daily optimization phase then sequential optimization again it will do multiple iterations and it will do a design rule fixing as we saw you will go back to the slides and make sure that whatever is in the story is actually appearing here then it will you see that it is working on the area recovery phase there is a worst negative slack of something it means that there is a time inversion here so now this is complete so you see that it is completed in one minute or so this is the area so during the delay optimization phase it saw the time inversion this is the time inversion this is the total cost so total negative slack of on the path that are valid we will see more of that later so we see that during different iterations here actually the area is starting to exceed from this value to this value it will exceed the bit because it is doing design rule fixing during design rule fixing it is maybe size of the driver it will add more buffers and also area will increase during delay optimization phase it will reach the WNS worst phase volition will decrease and also total negative slack will decrease this is where it is defining there will be an area recovery phase where you see there will be some area recovery phase here the area is reducing so we see that we actually see the priorities taking place so it will recover area but it has a reverse priority and it will first fix it will do a delay optimization it will pick design rules by fixing design rules it will make sure it does not so by fixing timing it will make sure it does not roll a design rule area comes last and so on this last one is the design rule cost so we saw that earlier there was some cost that means there was some volition there becomes zero that means it is clean so this will be compiled process now what we can do is we can write we can choose to write out the netlist we will see that okay give me a netlist right give me all the modules not that the top design and the output file write chip.v so now it is writing a it is right it wrote a netlist one it gives some warnings you could read more about it let's see it tells that there are some unconnected met which are named as this as with it let's see chip.v what so now it gave us different modules so usually the last one would be the top level so this is the last module in the file of chip.v again we see that let's look for the different modules so again there are there is a ramp you can see it the names are a bit odd I will tell you how to fix these names we see that there are certain okay it looks like it ungroups something so yeah so the number of modules we see here is much less than the number of modules we found this is the result of ungrouping so it gave a warning also here that it is ungrouping hierarchy let me see so this warning is it tells us that because the specified hierarchy is automatically ungrouped and we can so there is a variable it controls this so again by doing man and help you to get gather information so now there is this variable which is set to prove so I set it to false because I do not want to ungroup all the small all the small all the small blocks in your design you do not want to ungroup them for various reasons you might have problems so you could whatever you want to choose you can use this variable to control if you set this to false and then again to a compile I again to a compile the same option so every time to a compile or compile as that it will start from gtec again unless and until you are doing if you do not tell increment it will start again and now it does not give any warning it does not tell me it is ungrouping because I set the variable to false this is how you control the compile algebra by default ungroup small blocks but this is the way you can choose what to we will see that the area might be a might be slightly bigger than before only slide since we chose to keep the hierarchy so modern hierarchy will limit the amount of optimizations that can happen we saw that in the lecture slide because it creates some boundaries and DC will not optimize across boundaries we have also set boundary optimization to false we set no boundary optimization so again that will also lead us to so many times the trade off whether you want the lowest area or you want there will be many tools that will work on this netlist for STU you will work on this netlist for common verification you will work on this netlist so we will also have to think about that how do we make that process so many times we choose to not include the design many times we choose to switch off the boundary optimization because we want to make a problem here later in the play we will see that again I will write out the netlist I will overwrite that file I will again open this file and see now that now there are how many modules are there looks like it will not fix something but that is all right let us look at look more into this in the next section so in the next section I will focus on again I will do one more compile and I will show you the netlist without ungrouping I have to check that there was an error I have to check that it can be on the right window so in the next section we will also see now our designer synthesize now we will focus on how to report by his metrics how to report area how do we see what timing is violated how do we fix that we look at different timing looks how do we fix that how do we fix that and probably we will also look at the clock thank you