 Hello everybody, my name is Boris Yovanovich and I am Part of the lime micro systems I'm representing in fact lime micro systems and I will talk about adaptive digital predistortion, which is realized using lime SDR boards lime SDR boards that has lime LMS 7002 transceiver IC 2x2C and These boards also involves some FPGA hardware some altero cyclone for chip So I implemented this for this demo and I will show the results at the first I Will not I'm I first must to apologize Myself because I I brought here some Windows laptop Completely missed I I am waiting for 18 18 Zero you want to so until it Gets here, or I will use this. So sorry. I Had some problem with my previous laptop and I replaced it with this so Why predistortion is needed? Well, in fact power amplifier They are basically non-linear devices and their linearization is very important because they by linearization you achieve better power efficiency and the reduced you you should reduce your The cost of your your wireless infrastructure So I create some demo Which involves lime SDR board and some small Power amplifier it's maximum chip at and I intentionally put down lowered the Nominal power supply it which was 5 volts to 3.3 volts in order to get some distortions to be noticeable on FFT So this this is the spectrum. I use WC DMA waveform for for this demo and As you can see you have some distortions and the three distortions and They are because of this power amplifier and it's low power supply so I will use The distortion method that I have implemented within My hardware I will tell you after how I perform this Let me see Just I need to press Well, I have first to to get the samples from The board I have implemented in FPGA predistortion model So I receive the samples from that FPGA at The beginning at the input of predistorter output of predistorted and also in the receive path. I received three streams of data Three streams of data so with these streams I Do the offline calculation that's pre-formed on Intel CPU core so Predistorter implements all the mathematics inside But I received the streams from that predistorter predistorter and I finally Took the take these streams to get new coefficients To upload in the predistorter, which is basically like a filter. These are the results as you can see There's no distortions on the sides of the spectrum of WC DMA signal But there is some Drawback that there is some disadvantage. I Reduced a little bit power Power of the signal it's reduced for two DB's Someone can notice that that but that is because Characteristic of a signal which is called peak to average power ratio I should implement in predistorter model In in in front of this some crest factor reduction block which would deal with these signals with high spikes so when if if I I used both Predistorter model and Crest factor reduction ball block. I would achieve distortion removal and At the same time I will achieve the same power power level as original signal So in this demo I Get distortions out, but There is more the decrease I needed a little bit of Space on FPGA to implement these these blocks so All this is part of limesuit software Limesuit software is software supporting lines line LMS 7200 chip. I Just implemented some new part of the software Maybe Somebody of you have already been using this line software is for configuration of all line LMS 7200 chip. I just added some some new functions and DPD monitoring window and also I have also changed the FPGA gate were though So that is all for demo I Will stop jamming everything I will shut down this power amplifier and I will continue with the presentation so I so I will speak about DPD model and I will then Talk about some implementation Platform how I realized this and I will give some measured results with real hardware with real Power amplifiers Well For some Well, we usually Check some characteristics when we're speaking about quality of signals we find ACPR and EVM So when ACPR is reduced and EVM is improved we can obtain some complex modulation shams and We can implement higher bandwidths and Multicarious signals, so our solution improves the both characteristics both EVM and ACPR It's important to say this that this Solution is open source. It can be downloaded on github But that open source solution is implemented in fact for some other type of the board not this one one SDR, but one other called QPCI express which is 4x4 MIMO and With this board you can do the LLT stack and at the same time you you should run DPD with LT stack basically architecture is based on of Adaptive digital predistortion model, which is given in the figure You have two main blocks called predistorter and posdistorter You will you can see predistorter is implemented within FPGA in it performs Some mathematics past mathematics for example Every sample with the sample rate 30.72. I do some complex mathematics and Which is some something like some filter and The signal at predistorter output is predistorted in order to linearize the the following power amplifier So this this is some kind of baseband processing after the the samples are Upconverted fed to LMS-7002 chip Upconversion is preformed within this transceiver chip and after The output is connected to the power amplifier Post distorter block is implemented within CPU core within in the software in fact so That predistorter just takes the the race of samples of predistorter input output and The signal in receive path and with this stream of samples It calculates the new coefficients new coefficients are then uploaded into the the FPGA into the gate ver So it's some kind of iterative process We we obtain this That the the process converges within one or two iterations. So it's very fast But the thing which is not the fast in fact is communication I Have implemented that that streams are taken from FPGA chip. I Have some I have some I Can read some FPGA registers and take all these samples and According all that samples I can calculate and upload new coefficients So the model itself is based on Volterra series for modeling nonlinear system So the both predistorter and posistorter has has he has the same Have the same model and they share the same complex coefficients According to these streams we do the training which is based on minimizing Recursively square error So that algorithm just changes the the complex coefficients in order to minimize minimize the difference between the signals and add predistorter output and The received signal so At the end when the process converges we have two two equal signals the identity one X and The second Which is received this figure shows the implementation On line as they are bored we have FPGA LMS LMS 7200 chip LMS 7200 chip preforms up conversion and down conversion and a line as they are Preforms it it Preforms the the the predistorter so predistorter is implemented in a line as they are bored and also There are some other blocks for the data used for capturing the samples This board offers two DDR to memories Memory blocks and I used one of them to to store the samples So I have the option from my software to to to tell the chip to start Template to to start Recording the the array of samples into data to to memory and after that when I find out that that array is finished that I Can read all these samples and Took them into the the the software in software I perform all the calculations and after that I will upload The new coefficients in predistorter model, which is inside the FPGA So I have predistorter block Capture RAM blocks for predistorter input output and the received signal and all these signals are Transferred through USB port to CPU core which performs all these calculations Beside the modifications in game fair also created some kind of GUI, which is dedicated to DPD Signal yp is predistorted to cancel the distortion of power amplifier signal x It's a measure of power amplifier output as you can at the beginning. It's quite distorted after when distorted is Run you we have power amplifier linear linearized and predistorter output is Without distortion also we have Here the error between predistorter and polystorter output at the beginning of the process we have huge error and after when conversion Predistortion is is done. The the error is almost zero is it is almost flat line That error is presented on these figures with before predistortion and after the the predistortion so we have for testing Use several power amplifier first test case is power amplifier maximum integrated max 2612 Saturated power was 19 dbm and for that case we use single carrier WCD may test model one with the RF center frequency of 2.14 gigahertz the second case was power amplifier class J gun hemp and In fact, we we we used two amplifiers which are cascaded First maximum before and which is followed by the class J J and hemp amplifier the saturation power is Saturated power is 40 dbm and for that case we use single carrier WCD may test model one with Frequency set center frequency equal to 1.5 gigahertz and the third test case Is with our power amplifier 10 watt power amplifier we used We used 20 mHz LTS signal with RF center frequency 2.65 So this is the video first maximum iterate power amplifier as you can see before Predistortion is run. We have some distortions that are minus 34 dbc's and the EVM was 60.6 point 58 percent after pretty predistortion is implement is is Reformed We have some improvement in ACPR. Sorry It is minus 51 and we have EVM 3.20 24 so with predistortion we improve both EVM and ACPR Also, what I did not mention is that with predistortion you we can also improve not only power amplifier nonlinearity, but we can also Impact IQ imbalance of the transmitter this model Solves two things power amplifier nonlinearity and the other one is IQ imbalance Especially one which is the dynamically frequency dependent. So with this model we Implemented all this we solved all the both both problems The second test case is the class J GN HEMT amplifier Before without with ADPD ACPR was minus 43 dbc's and with ADPD it was minus 53 dbc's So this amplifier is consisted of two amplifiers Maxim 26 12 and gun amplifier with Saturated power or 40 dbm So with using of this you can make your base stations with higher range You should improve your signals significantly The third case was our power amplifier It operates in frequency range 2.1 up to 2.6 gigahertz it produces 30 dbm out of modulated power and it has two Parts pre-deriver and driver. Pre-deriver is based on GAS HEMT transistor and the other part driver is based on HEMT transistor 10 watt Transistor in which covers the frequency range up to 6 gigahertz We using this power amplifier. We tested two signals 20 megahertz LT and 10 megahertz LT signals and the spectrums are given in following slides So without ADPD at the start we had minus 40 dbc's and after dpd is preformed it goes up to minus 49 So we have 10 dbc's improvement. Also we have improvement in EVM That's the case for 20 megahertz LT signal and the second 10 megahertz LT case We have improvement of 11 dbc's in ACPR and also we have improvement in EVM so Finally to conclude our algorithm has been implemented on LIME SDR boards and we Verified it by measured results So it's capable of cancelling any distortion up to system noise floor and we used three cases First one is the most It's the most easy and Second one is more challenging since there There were two PA stages and the third one is the most challenging Which have two pH stages and PA stages and with much higher RF frequency and higher modulation benefit So that's my presentation. Do we have some questions? Super interesting. I'm not sure if I really understand everything. It's a little above my level of But I can relate it to the audio world and Distortion in the audio amplifiers. I'm wondering it's this was this work with every Every individual amplifier, even if it's the same model they might have different characteristics Yes, the system is adaptive Okay, is it up to it? Learns the characteristics characteristics of every amplifier and in fact tries to to to produce the inverse characteristics, so you you Finally got the the results, which is linearized You you you you pre-distort the the signals to To to make the inverse characteristic code of main power amplifier So and the system is iterative and it's kind of Artificial intelligence, but you can easily learn The the characteristics of any amplifier. Yeah, okay. That's makes total sense I mean just to comment on that it also It says that it's adaptive so it even compensates changes in the characteristics over time Right and of a temperature and so on so it's an ongoing process They are slow process slow changes. They do not happen often and suddenly but they changes during the time so that that characteristics are monitored over time and system very quickly adapts to that changes and creates the inverse characteristic of of amplifier or of the current characteristic of amplifier so You when you're doing the training Continuously, or do you if you need to adapt over time? Do you need to the training process? Yes? Basically, it can be preformed continuously with some period I Can I should not do it always? But after some time Depends on operating conditions on I I can do new training and update the coefficients How often do you need to do this? Like once a second or like once an hour? It depends on Prefer I don't know well, I Created our solution to to be able to Implement new coefficient coefficients for several seconds to two seconds. So it's It depends on real application. What do you have what? What's what's a typical CPU usage? And what's a typical FPGA requirement? well for FPGA requirement, I Need enough space for storing the samples I have Three three streams of samples need To make this mathematics. I Do not have I do not use so much samples. I need 16 kilo kilo samples for example so I need Just to to to make this array and After that to collect them it can be done offline interested in like in the pre-distorted part because like storing yeah, I mean you need space but more on the DSP side which is Real-time I avoid real-time. I avoid real-time, but you have you have you have a block the pre-distorted block, which is on the Yes, it Act like a filter, but training is done offline Training of coefficients you have pre-distorted block. It's kind of kind of filter, which is its own Coefficient and how many taps you have how many DSP blocks In pre-distorted. Yes. Well, I'm using Multipliers embedded multipliers 18 by 18 for example, I use for example 40% of these DSP blocks within a cyclone for chip I think 90 multi multipliers for this so it depends on 90 90 90 Multipliers, so it's not so big hardware. Oh see you Beside this multipliers you need some some memory enough memory to store For example, 200 kilowatts of data and after that you just read the data preform offline Calculations to find new coefficients and upload it again into the pre-distorted only fit on FPGA Yeah, well, that's only if you don't have enough bus bandwidth to stream Yes, I will time right well bus bandwidth I Use for some other things for streaming healthy So I spare that bandwidth. No, I'm saying like in general like if I'm not speaking about lime sdr Okay, okay. Okay. I on our restricts. We have plenty of bend this I in previous versions. I the colleagues provided me that streaming continuous streaming and that influence He had influenced on some other characteristics. They could not achieve bandwidth of LTS signals when this Stream everything so I spared the effort and I Have done it it offline. Just I need to store somewhere Them and after that to collect everything Yeah, I just it okay and what kind of Actual sample rate are you using for transmit and receive because if I remember correctly DPD usually needs at least like three times sampling rate So you know on both on transmit and receive side You see You should have the same frequency if you have transmit but you hear you need receive but doing the same frequency. So For example in this hardware, I am running that 30.72 metasamples per second, but in qpc express board I used a little bit higher frequency two times higher and with this higher frequencies 61.44 I used I achieved to To make predistortion running on LTS signals 20 make sorry, I'm confused so 20 meg LT signal requires 30 72 Megasamples right? No. No. No. No. No. I managed with 61.44 somehow, it's not so It I basically you you sample at 61 61 something mega samples and that's enough for all you you Transmit at 61.40 some 44 and you receive at 61.44 and that's enough for you to Yes, DPD is running or that frequency. I Store the samples after collect samples and do the mathematics upload the coefficients and that's it So that's the frequency which is I think good enough for good enough for 20 okay And what about the CPU usage? What kind of in a CPU usage to you? wrong for Post this torture Just floating point mathematics. Yeah, what kind of you know, I know what kind of CPU do you have? What kind of it's Well, it's offline and the most of time is spent on Getting the samples out from FBGA after I do the mathematics Very very very fast and upload the coefficient also very very very fast So it's not so important. It's relaxed It's like I do not upload new coefficients so often. I do not need that Yeah, but I mean, yeah, okay So it's not so so You mentioned that it takes two seconds is it two seconds to actually do all the mathematics Or is it two seconds including the most is to receive the samples. Okay, I Mean the the the post Distortion computation on the CPU that's like a low priority background tasks. So I think it doesn't really matter so much. I mean No Of course, it should you should be done as background task If you only need to like redo the training like every minute or so or longer, it's okay It doesn't matter if it I mean you can run that as the lowest priority on the on your CPU. It doesn't matter Yes, yes, of course, you don't have to run on CPU with high performance Just I need the floating point of mathematics within that CPU and everything would be okay One question I had though is that because you're using the Eric's channel to receive what you transmitted Uh-huh, what then all this your LTE base station works if it doesn't have Eric's anymore Base station, so I this is only for demo. Yeah, of course What solution do you recommend? Well qpc express boards? So in the receive part one receive part is dedicated to dpd and the other would be dedicated for For example for performing LT. I have implemented on some other boards But can they be tuned to different frequency the two the two erics chain? On different frequency you get to LMS 7002 chips. Oh, you have two different LMS chips two different LMS chips on It's not using this the dual channel of the LMS. Yes Yes, that's the trick this one is only for a demonstration and It has one chip and I cannot run LT at the same time running DPD you can probably do tdd mode Yes, of course Which is also Right, we're using td Tdd is very popular. Yeah, China is all tdd India is all tdd. I mean How does the because you said that the So this guy this algorithm can also compensate for the like imperfection of the IQ imbalance, for instance You transmit. Yes, but how does the IQ imbalance of your erics influence because you're gonna Your algorithm is gonna try to compensate for something that isn't really on the Yes, good question I cover our spot at the same frequency In perfection, so receive pot in that DPD the receive we have one real receive pot in the in the other chip so we can Influence only to transmitter pot, okay any more questions No, okay. Thank you