P4-Enabled NICs - Acceleration of OVS by Petr Kastovski, Netcope Technologies





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Published on Nov 23, 2016

P4-Enabled NICs - Acceleration of OVS- Petr Kastovski, Netcope Technologies

P4 provides a way to describe custom packet processing chain that involves header parsing, field matching, decision making and assembling modified packets. The language is target independent and can be mapped to CPUs, FPGAs, NPUs. While originally intended for use in (possibly virtual) network switches, P4 may also find applications when integrated into servers’ network interface cards. In this talk we will propose several use cases utilizing P4-programmable NIC to accelerate/offload packet processing in concert with the network and applications, such as traffic steering to CPU cores, filtering, en/decapsulation for VNF chaining. Regarding implementation, we will provide results of our ongoing R&D efforts towards fully P4-programmable FPGA-based 100 GE NIC. Making full use of FPGA’s structural reconfigurability and massive parallelism, we were able to achieve throughput of 100 Gbps for most packet lengths. Through the talk we would like to initiate a discussion that would bridge the gap between OVS experts and NIC designers and programmers with the goal to accelerate OVS using P4-enabled fully programmable NICs.

About Petr Kastovsky
The presenter is Petr Kastovsky, CEO of Netcope Technologies. Petr has worked with FPGAs and their applications for past 12 yrs. Starting with R&D activities at university and then leading a development team in start up company that evolved into a leader in FPGA-acceleration of high-speed network data processing and being the first vendor to introduce programmable 100G network interface card.

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