 The other possible gate adder of course, some I will show you can read these are fundas and therefore, I thought maybe you should look into them seriously here is another gate which is called transmission gate adder and we all know the transmission gates logic per se CPL as it is called complementary path logic or just pass transistor logic as least transistors because this it does not use normal NAND Norse directly it essentially uses muxes in some way. So, here is a transmission gate adder one of the some part requires your XOR. So, I have shown you an XOR circuit it is very interesting you can see from here this is your transmission gate P channel device parallel to N channel device this is your transmission gate then you have a inverter like structure made of P 1 and N 1 essentially it is also transmission gate, but essentially you can see it is like behaving here as inverter. The upper drain source of this P channel is connected to the input A please take it the source of P channel is connected to input A and the source of this N channel is connected essentially to the output of this and to the gate of N 2. The P 2 gate is also driven from A input now you say why I did this of course you can see if you implement you will find very clearly let us say A is 0 and B is 0 and you expect output to be 0. So, if A is 0 this transistor is on. So, this node is 1 if this node is 1 N 2 is on I repeat if A is 0 this P channel is on V D D comes here 1 appears N 2 turns on. However, if you look at B which is 0 this P 1 turns on P 1 turns on, but this voltage is 0 please take it A is 0. So, the source voltage of P 1 is 0 input is also 0 P channel will be on, but the node it will go to 0 if this node goes to 0 obviously even if this is on B is also 0. So, it transmitted through this 0 it also came 0. So, no contention the vary was contention no contention both side I am stabilizing 0. So, the output goes to 0 which is my A X or B for 0 take one at least one more A is 1 and B is 0 and I expect out to be 1. So, if A is 1 N channel is on this is 0 N 2 is off N 2 is off. Now, come back if A is 1 the source of this P 1 is V D D since B is 0 P 1 is on if P 1 is on and this is V D D this is V D D 1 since this was 1 P 2 is also off please take it N 2 was off because it is 0 P 2 is 1 in gate is 1. So, it is also off. So, B is not influencing output now it is only from this I got my V D D. So, no contention. So, I got 1. So, how many transistors A transistors. So, you know by this is an XOR same way other A B B C functions is implemented here shown here. So, by using 4 transmission gate 4 inverters 2 XOR gates and adder can be constructed which is shown here. So, what is the advantage we characterize this of course it will require area. So, many transistors 24 transistors. However, it has equal delay for both some and C. So, that is very good it is equalizing the delays this is same operation if you use this is AA bar this is CCI bar this is my XOR and this is my sum generation and this is my Kali generation. Symmetric circuit very important symmetric circuit all times designers must see that their layout is symmetric and to make layout symmetric make your schematic symmetric because only then layout will be symmetric. Taking the same queue we went further we said ok if you can use carry transmission gates pass gates. So, instead of using A B C I can now use G's and P's which we have or G and D's and I can generate both carry and sum. So, here is a carry generation I have A input C I which is passing through a transmission gate under control of P I this is generation bar which is essentially delete and sorry GI bar and this is delete. Now, let us see what happens if P I is 1 we know GI is 0 always please take it a P is 0 P is 1 G must be 0 A XOR B something 1 A B must be 0 that is XOR equation. So, if A is a P is 1 this is on P is 0 P I bar is 0. So, this N channel is on or P channel is on N channel C I is entering C I is entering. So, C 0 is C I that is the function we wrote G plus P C I a P is 1 G has to be 0 C O is C I transmitted. So, we can see now if C C let us say P 0 is 0 if P 0 is 0 the pass gates full pass gate is off P channel is off N channel is on because P I is 0 means P I bar is 1 both P and N channel off no carry can enter. Now, look at it if GI is 1 that is GI bar is 0 now carries G we know if P is 0 means carries G. So, if G is 1 that is A equal to B 1 then GI bar is 0 if GI bar is 0 P channel turns on we really appears which is 1 transfer by same logic if A and B are 0 then this will turn it on this will pull down C 0 will go 0. This is essentially what this word Manchester carry did then we figured out that this is a static circuit in some way, but not used in a static mode. So, why do I use to pass transistor instead I will use that in series of this and use dynamic gate. If you are you do that this is some kind of a partial latch I can say and I use that trick of latching where I can block the output by 1 pass so I use that then I say now only thing trick is I have to input C I bar and we know how to create bars every such case actually you create bars. So, you do not worry too much getting bars you have 5 5 5 these are P channel N channel device which are clocked with 5 and you have generate signal here. Now, one can see if P I is 1 this is on whatever is C I bar is transferred to C 0 bar that is C O is C I that is what we always say when the P is 1 C 0 should be C I so that is transferred if P is 0 we know C G. So, no carries entering P 0 means N channel of no carry enters. Now, we look at it if 5 0 initially this node is precharged to 1 this node is precharged to 1 because this N channel is off this P channel is on this N channel is off when I evaluate 5 goes high this 5 is also goes high. So, P channel turns off and now this transistor is on depending on G I that is a b is 0 or a b is 1 this transistor be on or off if G I is 0 this will the mean V D D precharged that is what bar you wanted carry bar. So, you have obtained it if you expect G I to be 1 that means a b is 1 then this transistor will turn on this is anyway on this will pull down to 0 which is the opposite of 1 anyway has occurred for you. So, this is called dynamic implementation of Manchester's carry essentially they are all dynamic gates clock gates they actually have their own problems, but I think my course should not look into those problems right now. So, if I now connect number of them 4 bits 8 bits 16 bits any number all upper P channels or gates are connected or lower N channels gates are connected to 5 both sides at this this is my C I 0 first and remember only difference it in the first case is C I bar you have to substitute and you can see here depends on a and b that is B either C whichever you expect will come this will act like a input for the next and you are actually taking this output immediately as inverted output as C 0 C 1 C 2 C 3 and you can now keep propagating your carry depends on whether a and b are what depends on here these are 4 bits a 0 b 0 a 1 b 1 a 2 b 2 a 3 b 3 and a n b n a n minus 1 b n minus any numbers stain, but this looks very simple noise everything is nice. So, if you see is delay this formula probably I do not know how many of you still remember it is called Elmer's theory it assumes right now that P channel is a resistance obviously because passing some current it is like resistance and all these transistors their inputs are at the capacitive. So, we say it is like a RC network this transistor is parallel to this at this node. So, all are so you can see this is a RC transmission like network and using Elmer's theory typical time constant associated with this is 0.69 n into n plus 1 times R and C is for each this is R and C by 2 averaging because extra stage. So, n plus n plus 1 by 2 into RC now one can see from here in this case we have assumed as if things are going very well this is what I say more technology more worries I mean either I say 60 year old person has worries you may not have you may actually enjoy doing it flip flop. So, if I see delay from here one clearly sees that as the bit size increase the delay will increase because the so many if in a transmission line the number of RCs are too high that Elmer's theory says it keeps multiplying. That means this is not very ideal though it looks very good for implementation because it looks so simple to implement. So, we say this is good we did not say much on this I can reduce probably R and C by choice of the transistors are used both P channel and N channel I can actually put minimum size larger size, but once I put a larger size for R and C if I put this larger for good drive you see remember I am to driving a huge line. So, I need a larger transistor larger transistors larger capacitance. So, my I may reduce R by increasing size by my may increase the capacitance if I reduce the capacitance by reducing the size then I increase the resistance. So, essentially RC is never improving in any such systems. So, if larger and anyway you are spoiling further the length depends on the bit width you have you have a large delay coming from wire it may actually exceed all other delays. So, where he starts how to do that essentially for a VLSR one can always see the wire delay will be always smaller if the width of that line is larger resistance will be smaller. So, all the time whichever line is running for smaller arc you expect the wire resistance should be reduced if you can widen that out, but widen has another problem the capacitance which will get also will enhance. So, the you need not use normal oxide if you have a low K dielectric as what we do in interconnects use those. So, never use the first interconnect line for any such RCs go on the higher levels and you may improve your R and C of course, there is additional R coming through via, but that may not be offsetting too much. This is the implementation this is what I just now said capacitance per node on a carry chain equal to 4 diffusion capacitance 1 input capacitance from inverter and 1 wire and wire is the major capacitance some day you will find as the lower technology starts. That is why if you have heard today or yesterday major worry in VLSR design is not on so much on gates, but more on interconnects. So, it is now the new word has appeared they call interconnect aware designs you should be aware of interconnect more than anything else. We use this trick slightly in a different I am this I said fine I can now use another adder in which I may actually skip the carry. Now, this is normal ripple carry adder shown here 4 bits this has inputs p 0 g 0 this is p 1 g 1 p 2 g 2 p 3 g 3 that is a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 kind of inputs. So, what essentially this ripple carry we did we say we are just that is I keep saying that formula is always in my mind c 0 is p g plus PCI. So, I say p is 1 g 0 g is 1 p 0 that I know very well. So, I figured out a x or b a 0 x or b 0 a 0 a 1 x or b I know all p 0 p 1 p 2 p 3 a priory because I will actually generate them. If I have that value known and if all of them are 1 I know the it is only if p is 1 g is going to be 0 anyway and whatever is the carry I am pushing that is the carry I am going to get. So, I use whatever this 4 bit adder I added another line connected to a multiplexer this is the carry which is may be generated in other cases when p 0 p 1 1 of them is not 1. So, I have a 2 muxes and I have a excellent which is product of p 0 p 1 p 2 p 3. So, if any one of the p 0 p 1 p 2 p 3 0 which will selected the upper one will be selected that means you are actually carry carrying through your this which is a normal carry generations. But in case there is a case when p 0 p 1 p 2 p 3 all are once this lower is selected for the mux and lower is the input. So, transmit. So, it automatically at least some part of the circuit where your input data is such that p 0 p 1 p 2 p 3 are once you do not have to generate c and directly pass and this c is available to you for the next stage even before sums are calculated for this full adders because it is bypassing all of them. No timing is required for this full adder calculation of c f p 0 p 1 p 2 p 3 are once. However, if they are not then the normal calculations need to be performed. The trick we use then we say if you have a very large amount of bits adding to do 16 bit 32 bit 64 bits. So, I said what I will now do since I have to use muxes I break those number of n bits word which is I am going to use into m blocks. So, I have m part of n. So, let us say in this case m is 4 I use 4 bits m is 4 and let us say I have a total of 16 bits. So, I now 4 blocks required for each block 4 bits. So, I have for 16 bits I need 4 blocks repeatedly please take it this part is same as what I showed earlier. So, I said the first thing is let us see what is the total added time let us look for the critical path. The critical path starts from you have to generate a 0 b 0 you must get a 0 b 0 c i minus 1 of course, c i is coming here and then you generate p and g that is called setup. Setup means generation of p and g is called setup. So, I generated. So, there is some time I will spend in actually generating p and g. So, that is called setup time then using that setup p 0 g 0 on the 4 bits which I did just now 4 adders add carry and I see if any one of the input is 0 p 0 then it will pass through this propagation if not it will pass through the other side and be available to me. So, I have a time if this directly passes there is hardly any time, but this time plus max time is being used by me to generate the next c. Then by same logic when I get to here or here I am using this block, but here the setup time is not required by because when I was setting them all I have set. So, I am not putting any additional time in setting p 1 p 2 g 1 g 2 any one. So, what is the critical path setup time then this is that bypass part whatever is the this there is a carry, carry whatever the time taken for carry that part is inverse case let us say none of them are passing through directly and all have to do. So, you need that much and since there are m bits m times each of them will require time. So, m times t carry plus there will be a time for max which I say is a max this is called bypass is essentially max time to pass through a max. Please take it this time this time plus time for a max and since there are n by m minus 1 max is because 1 2 3 are required forth I do not need to get the sum final sum I repeat I do not need 4 maxes I need 1 2 and 3 to get the sum the next box I am not using for this side. So, I need only n minus n by m minus 1 only. So, I say m carry plus m minus 1 t carry which is the other side of this plus sorry not m this is the n by m minus t bypass. Now, this carry is generated for each of them each of them. So, you have to add that was please remember this is the worst case calculation not that every time this may happen many a times you may actually go like this. So, you will be speed up, but design has to be for worst cases plus the some time which come here. So, the net time is this and this also shows larger the number of n larger is delay, but at least it is not it is also can be divided by m. So, if I choose my m blocks properly I do not know how much increase in t carry I will get because depends on m and n choices I can optimize the delay little better I repeat our 2 parameters to optimize our n and m. So, I adjust the 2 such that I get minimal delay. So, if I compare carry ripple versus carry bypass putting all others time as equal all equal t sum is equal to t carry equal to everyone is say minimal then I plot bypass time versus n bypass adder time versus n and by ripple adder. So, you can see the intersect at some point of course, that depends on the other values, but for one value of equal I have chosen or rather Ray Bay I have chosen. You find somewhere here around 4.8 or 5 they cross what does it tell if your bit size is smaller than 4 use ripple carry. If it is more than 4 go for this bypass adder. So, this when to use when so of course, this number may not be exact because the other values will decide where it will cross over, but the idea is to show that you can find some optimum below which you should always is ripple carry above which you can use bypass. The third possibility is select carry select all that time you are using that carry may be 0 or carry may be 1 and so depends on 0 or 1 you are transmitting something. So, I said here is another game I can play I said I generate my PNG as usual and I actually calculate carries both assuming input carry either 0 or 1 there are only 2 possibilities. So, I do calculation a priori assuming either it will be 0 or it will be 1 for given P0 G0 P1 G1 whatever it is I will assume both possibilities and I will calculate them both of them and then I will connect them both to a multiplexer and depending on the actual carry I get I may either choose this or choose this. So, I said sometime this is a priori operation. So, I said I can select my carry and selection is essentially from this and then finally, some can be obtained and final new carry can be generated. Now, if you see same 16 width adder for carry select this is again same operations no difference. Now, you have to what is the critical path now you have set up 0 carry 1 carry multiplexer then this multiplexer and some. So, there can be 2 possibilities one is that I choose M which is say 4 4 4 equal they are 16 width I made 4 blocks 0 to 3 4 to 7 8 to 11 12 to 15 4 blocks the other possibility is I may choose some other number first 2 bits next 2 bits next 4 bits next 5 bits kind of this I keep increasing bits as I progress of course, you can see you will need some additional blocks in most cases, but that is a part. So, now if I use this kind of architecture in which I want to know whether now the delays are different one method is equal m's alternate next is m m plus 1 m plus 2 m plus 3 m plus 4. If I do this calculations for the first case it is set up time n by m times t plus t carry plus t sum as usual however, if I do different bits 2 3 4 5 like this I have a net n is m plus m plus 1 plus m plus p minus 1 p stages p are the stages earlier n by m is was known now I am not saying same m is varying now m m plus 1 m plus 2 m p plus minus 1 and if I expand that the series sum of this is p square by 2 plus p m minus half this is a standard series sum this is a series and if I see very carefully that if n are very very large this roughly becomes p square by 2 p square by 2 this term is then very small there or we say p is root 2 n. So, this stages now you have which you have is earlier how many it would have been n by m stage now it is root 2 n and if I now write the again same expression for time it is t set up m t carry plus root 2 n into max time plus t sum in earlier case in linear it is n by m t max you can see now the lower one t add is proportional to n the upper one is proportional to root of n this is kind of logarithmic system I created and therefore, I can reduce the I mean improve the speed or reduce the time. So, if I do this equivalent again I have so you can see from here if n is very very high square once almost tapers down is remains constant. So, if you have a 64 bit processing something is doing always choose square root kind of things that is used increasing this however, the hardware is higher as you said yes, but that is the penalty I paid to improve my speed otherwise use linear if it is little lower and if it is much lower 4 bits or something still use ripple carry the last of them look ahead all this problem we looked into point of view that you have to generate carry and it has to propagate carry. So, we came out with an idea that look at our functions maybe I think this second sheet can be better just do not see figure right that is what I say my hand drawn figures are something like that you know. So, if you see the carries the first carry is g 1 plus p c 0 see the input carry next time if you see it is g 2 plus p 2 times c 1 p 2 times the last carry, but c 1 I know what is g 1 plus p c 0. So, substitute in the second my c 1 term and I expand it so I get c 2 is g 2 plus p 2 g 1 plus p 1 p 2 c 0 if I see c 3 it will be g 3 plus p 3 times c 2. So, I put c 2 again in that function and I again expanded so I get g 3 p 3 g 2 p 2 p 3 g 1 p 2 and as many carry blocks you have. So, if you see your last carry part from a block do you see you actually normally what did I say the initial carry is normally 0 initial carry of a first adder is normally 0. So, you can see the final carry generation is almost independent of the carry you are actually having it. So, all that you have to generate is g p g p and if you can generate them one after the other then you have a situation in which you can generate c c 1 c 2 c 3 c 4 without actually having full knowledge of c i if you have a c i I mean one calculation is there, but most times you may sign you have a generation is very fast you are not dependent on the last carry please remember you are not depending on propagation of the carry you are actually looking ahead of the carry itself. So, here is the output carry is related to g k plus p k g k minus and series of them you can keep expanding them till c i minus 1 that is the last input carry. This can be implemented by simply this kind of circuit you have 4 p channel devices here 4 n channel devices here all n channel receives p 0 p 1 p 2 p 3 all p channels here receives g 3 g 0 g 1 g 2 g 3 and this in between these 2 receives input carry. Now, we can see depends on you know this implementation is not very good, but just to get an idea 4 transistor here 4 transistor here if you have more bits on that how many series transistors you will see 4 5 6 this and all such systems will be always slower because you said by reducing this look ahead we do not want to propagate we saved the time. So, ideally we did, but in real life if you see a CMOS structure your capacitances will be so high that essentially your logical effort went up. So, this ideal thinking what the formula shows is not really valid if I really see implementation the way I will understand is this in a domino. I have this upper p channel transistors here and you can have multiple n also, but I have shown 1 this should be larger size to sink enough current. So, the way I did first input carry and first p 1 in the first vertical line this line and the output is we can know the output of this is c 2 or c whatever it is c 1 for example which is PCI plus G. So, every time I am you what function I am implementing G plus PCI ok G plus PCI. So, I say this is PCI series to that is G. So, put immediately p 2 for this go above put G 3 on this keep doing, but you can see here also for every 1 of them if you see the path actually it is series connected by showing your 4 lines I tried to show you as if they are only 2 in series 2 in series 2 in series, but in real life for the last one the path is this the only thing is since I have already evaluated them before I reach there sometime I am trying to save by combining them ok, but essentially larger n will require larger time even if look ahead people feel there is no carry propagation even then there is a propagation going on because I mean speed is not improving so much as we thought had to be. Also each output of G from where it is coming where the final fan out capability may require larger transistors also larger fan in will require improve or rather increase the logical effort larger fan out will require larger speed down there also. So, in some sense the look ahead which came out with a such a band saying that oh I am now fastest adder with me did not prove to be as good when I really implemented it, but we are not we will not leave it say ok here is another possibility we say delay is proportional to n in the case of look ahead if we do the operation which I showed instead I make it a block decisions ok I say ok I will make a block of 2 or 4 or something I do 1 calculation for something which is faster on some other and then for each of them and then propagate in between them ok this is that what I might say I did broke in 2 parts a 0 a 1 a 2 a 3 as this I perform operations for 4 blocks and then again 2 block and then this block this essentially is like a tree and one can will show you that then the delay is proportional to log of 2 to the log of n to the base 2 essentially what we did if you are 16 bit numbers 2 to the power 4 is n. So, I need to calculate only 4 such positions the delay and I will be able to then calculate the delay directly this is the method now what we did ok maybe there are different kinds of look ahead carry available one is called ripple block carry look ahead what we did we make blocks right now I showed in the 2 blocks. So, blocks of 2 bits 4 bits kind of thing. So, in a block I use look ahead in a block I calculate delay because I know for n lower it will be faster. So, I use n lower and I calculated the delay using look aheads, but between the blocks I actually ripple between the blocks because then if n increase I know it is not very. So, I ripple it. So, this ripple block carry look ahead adder the idea of the ripple block carry adder addition is lessen the fan in because then you do not have to put larger inputs smaller inputs and lower fan out difficulties. A ripple block carry look ahead adder consist of n embed blocks arranged in such a way that carries within blocks are generated by carry look ahead, but between the blocks I ripple it that is what I said I just read again. The block side m is normally fixed no more than 4 because otherwise logical effort will be very high ok. So, we normally do not exceed m more than 4 if you do that then it can be grouped in a 4 and then any number can be done and it will be log of that those points can be obtained. This essentially is called dot operators you know for example, a parallel prefix adders are constructed out of fundamental carry operator which is called dot operator C. So, if you have a g double dash p double dash then it has a dot product with g dash p dash this is a group of g and p. So, instead of g 1 we say g 1 g i p i is one block g i plus 1 p i 1 another I keep blocks in my design and if I make a dot product the dot product of this essentially is g double dash g double dash p prime p double plus i using this may be even better figure can be shown. This is essentially a dot operator as I said time permitting as we can explain. So, I can now work on a block design here we I can go for look ahead and block to block I will ripple anyway and using this concept as I say the many adders have been published one is called cork stone then this kunkts tree valestry many trees which you see essentially are doing this what they do this is a block of 2 for example and each is now transferring to the next level by ripple here is another one for 16 this is the 64 bits you can see the way I assume this is a block of 4 block of 4 block of 4 and then they transfer as a 1 to the next block. Take a block 4 transfer to the next as 1 1 carry and keep using for next. So, for then next 4 then 4 you can see then I am going logarithmic way and therefore, I can speed up my operation in the look ahead carry. So, look ahead carry is never used in a normal way if at all it will be one of the 6 or 8 trees which are available. Last part we can also do much of this hardware using dominoes because that has an advantage of less number of transistors. However, you will require a keeper this inverter which is a weak P you need this block to keep this circuit not trying to go out of the logic this called keeper. So, you can have a generate propagate on a domino you can also have a sorry same figure has come then you can use both of them to create your domino sum. The last part quickly I will say it is a carry save adder. The carry save adder is essentially a serial adder carry save adder is called is a serial adder because if you see your earlier figure which has shown a serial adder what was serial adder was doing that you input the data as origin from somewhere and the way it happens it takes the last carry adds with this finds a sum and recirculates back through a register. Now, that fact that it recirculates that back essentially is a serial adder carry save registers both carry and sum together that is what serial adder it is register sum and registers carry that is why these are called carry save these adders I am showing you because I talk so much on DSP these are the ones which probably you will use mostly in a DSP applications. The way it is done there is a sign input there is a carry input first a input is added here and then transferred to the so this part has two layers one can say which is delayed by registers here. So, this operation is performed pass through registers to the next block where B input appears and then final sum is carried out parallely. So, the first block is called carry save adding and the second block to get full sum is parallel adder is a parallel adder. So, did I did I tell you initially that never work for serial or parallel try with serial parallel in case of DSP is serial parallel adder is very important for saving time as well as power and therefore, these are very important as I said time other we would have discussed much more details just to give an idea typically carry this carry propagate adder which is shown here the way it is a b a 0 a 1 a 2 a 3 are shown as a inputs here. So, the way it happens the first addition is performed and it is delayed 3 clocks, but the output of this carry is through a register is given to the next stage the output of this carry is given through another register one other delay to the third stage output of this carry is given through another this and since this carry must wait because it will take 3 cycles to come here I will delay my last input by 3 cycles because that carry will take 3 cycles to reach to my this place you can see 1 2 3 1 2 and 3 delays to come here. So, I actually for a 3 I actually delayed it by 3 clocks. So, that it actually coincides and I get the new sum this essentially is it is used in a DSP because it of course, it has a very DSP does not bother too much on latency, but they want outputs. So, you have large outputs you can create you can fill the flip-flops by data you can serially keep coming the data it will move in a clock cycle as after 3 clock cycle this will be operating after 2 this will be operating after 1 this will be operating. Now, the data is keep coming and since it is keep coming you are it is like pipeline pipeline is full the latency is k plus 3 k is the time for addition per cycle. So, actually latency has increased, but the throughput is very high and speed is not governed because speed is now decided by the clock. So, these are essentially pipeline adder this is that Nora implementation Nora is essentially domino sum extent or zipper in which n channel device or block is followed by p channel n p. So, if this is p the next is n it is called n p or Nora. So, this is essentially only 2 bits shown here there is another adder which is called conditional sum adder. What we are doing using a pass gate I can create s 0 s 1 c 0 c 1 and these are functions are called generate s 0 is my x norm s 1 is x r c 0 is a dot b c 1 is a plus b. So, all 4 functions I can create then what I do this cell I call is a conditional cell in which I can create all 4 and depending on actual carry I will output the sum it is conditional what carry put that output. So, essentially by you can connect sorry you can connect actual outputs depending on switches you can put this can put this. So, I can decide whether carry is 0 I will go up carry 1 I will go down. So, this is called conditional sum it is used in many applications for saving actually hardware. We will quick list I was just trying to show you that all adders find the maximum use in multipliers these are some of the multipliers this you can try this is the easiest multiplier which uses some kind of serial business and parallel adding. You are inputting data serially, but using addition parallely this is called shift add register shift add type of multiplier easiest to implement of course not very fast for fast multiplier you need arrays you need lot of half adders full adders you know and the kind of times you need to know. So, there are different kinds of multipliers to show you which will improve the speed both of course is the best among them, but everyone is using adders all that I am trying to show you that they are using adders huge adder blocks. So, if you have a 64 bit adder this is unit then you can see carry bypass will be 0.27 carry select will get 0.27 carry look at will get 0.15 provided it is logarithmic kind and this is the graph for that different adders I have used for different n you can see static highest mirror Manchester bypass select depends on the bit size you can make a decisions same numbers are used in the multiplier and this is the decision for multiplier final I thank Mr. Rayway Chandrakas and the colleague for their effort in explaining the arithmetic in their book which is chapter 13 digital and circuits of course to my students who made many of my transparencies which I did not show fortunately except one I did not show many of my transparencies many post graduate students which I keep saying I learned much of my hardware and software software I do not know from my students if Anand who sits in my class ask me a question then I think and maybe that time I said I do not know but next day I will say what this is how it is so I think I am helped by my students and most of us are so that is a catch word if you do not know a subject teach it because when you teach you learn and finally thank you all for patient listening and I hope that something you learned here was worth spending time at IIT Bombay these are the references please take it this is just to show you whenever you use others this this kind of statement was adopted from UCB course site which is a copyright of Professor Rayway from and also from the book which is Prentice Hall 2003 edition also from a strong in and West also from for DSP anyone interested Professor was Sharma teaches one times of scores system design we use a book which is written by Indian Vijay K. Mendisetti which is VLSR digital signal most of the DSP part has been picked up from this book and also of course some arithmetic part I picked up from compiler arithmetic very old book Vang's book and so when my students were working we looked into many of these these are essentially the four books which this particular part was using there are many good books other than this but these are something which particularly slides of mine and talk of mine has compiled through. So, please as I say most teachers use slides from anywhere it does not matter as long as you are not selling this allowed but first specify everywhere on every transparency if possible whose index is there or at least right of course this they expect this first line to be at the first they expect we start with this adopted from this and then show any slide. So, in case you are doing this please do this otherwise you are violating copyright act and you are punishable of course it is very difficult for Americans to come and sue you here so it is okay so you can get away thank you very much.