 Here we go last time just we started looking into operational amplifier and we said the first stage of an operational amplifier is a diffam differential amplifier and if you have used the opamp recently you have seen that there are two terminals one they called V minus the other they called V plus are essentially the two input terminals of a different okay. So we have already done something but I just want to recollect so you can see the input to opamp is essentially input to a differential amplifier. Now this here shown here is there is only one output there is a possibility that it may have two outputs so call it VO1 VO2 and I can actually take a difference between the two and can get VO1- VO2 as my new outputs okay or I may see I only get one of those outputs the other is not relevant the way I do as in most opamps and we say that is my VO that one small thing you must understand the circuit shown here or the symbol shown here does not have any connection between V0 and Vn except for the capacitances because there are CGDs and they will give some connections so there will be poles and zeros associated all the time even if we do not say they are capacitances however in all opamp circuits barry exceptions are the same there are no internal capacitances CC1 CC2 or CC there is no such capacitances present in any operational amplifier so what is the advantage of such system what is CC1 CC2 we are doing they were decoupling DC and AC so the trick here is now what I am saying that an opamp can also receive DC inputs is that correct opamp can receive DC input all we do not amplify DC what do we amplify only AC signals but is different from all normal single ended amplifier defam is or different opamp is that one can amplify DC signals is that correct that is the major difference between normal single ended amplifier which are small signal AC amplifiers so if I really plot the border plot for that what will be the typical gain you will see from here if I played gain versus frequency at 0 frequency gain is not 0 or not following so typical characteristics of a border plot will be something like this even at DC 0 frequency there will be a finite DC gain now this DC gain is same as what we say otherwise DC gain okay so that is the major difference we should understand that in the case of opamps or in difference even at DC outputs are possible is that correct so in all my analysis ahead why I am showing this I am actually not differentiating too much between small ID capital ID so I may use a term like ID which actually takes care of AC plus DC or only DC or only AC as if I am having some signal which is getting at the outputs okay is that clear to you so that is like symbolization sometime because you know we have been talking single ended amplifiers small signal ones and we are very categorically saying small small small we say input AC is only okay here we may see what is the difference however normal gain of this amplifier which is a small signal gain is still an AC gain whereas the DC gains are not possible if this circuit acts what will happen if there is an input signal between this input terminal the output because there will be large gain of an amplifier the output will go where gain times the input where it will go very large value but the maximum value available to your what maximum minimum VDD and VSS so actually the output may become either VDD or VSS depending on this is higher or this is higher is that clear what is this circuit should be called therefore I have two inputs if this is higher this goes to minus VSS if this is higher compared to this this goes to plus VDD comparator so I can now use the same opamp if I compare the two inputs depending on the output whether it is VDD or VSS one can declare VDD as 1 minus VSS 0 and therefore it is like a logic block a two input signals can be compared and the output can become digital 1 and 0 is that correct this is the advantage of opamp over normal single ended amplifier and therefore we want to know what exactly goes in why how this is possible and that is why the present thing we have started with differential amplifier is that clear why we are so keen because every other circuit in future will use opamp and whether it is A to D converters or D to A converters or any filters everywhere will use operational amplifiers and since we are going to use operational amplifier the first thing we must know what it contains and why it gives such a behavior which we can then utilize I heard in systems is that okay so this issue which yesterday or debut first I did not say I thought I just started if I am because it was evening I mean let late in the class I thought maybe that time I did not spend time but you must know my context why I am doing this I do not do anything here which I do not think I will use later unless I have some reasons to say okay I will I know it is important but I do not want to use it right now I say whenever I do something it has a repercussions ahead that is why whatever teach today will be required tomorrow tomorrow is next okay having shown you the operation characteristics operation amplifiers so also one interesting feature about this opamp is this which is also interesting to show you because if I plot Vo versus V in of a operational amplifier depending on if I can ground this and take a reference minus V in also can occur so I will find sorry it will cross to 0 there is a range in which for minus V in or plus V in the output will be high I mean linearly follow it and at certain higher input signal it will start saturate so even in open there is a limit up to which input swings will be allowed to have larger outputs beyond which what will happen they will saturate and then what is the essentially whenever the output saturate what is the gain is 0 essentially it will never reach 0 but it will be a very small gains will start coming closer to 0 and because of that the outputs will be nonlinear and nonlinear if I expand it in a Taylor series or Fourier series then I will get different frequency components omega 1 omega 2 omega 1 2 omega 2 omega 1 plus minus omega 2 these are called harmonics okay so if you operate somewhere here not only omega 1 your major frequency output will appear which will be much reduced because part of the power will be delivered to other frequency components is that clear so one does not want to operate in the saturation around saturation region so there is a limited range even for DC is that correct even for DC there is a limited range in which amplifier will act like a linear amplifier is that clear otherwise it will be a nonlinear amplification in which it means that other frequency component will receive started the thing power okay this fact has to be understood that even opium I keep saying DC it does not mean 100 volt I apply and I will get 1000 volts because if that happens it would be a great thing you know with a small device I can have generators put everywhere and the houses and I can supply power without any power coming from anywhere else such a thing thermodynamics will not allow so therefore there cannot be such energy creation without any other creation giving energy so do not believe that it will have infinite ranges it will have limited ranges for amplification as well yes no because linear region is sin omega t term all sin omega terms will only get amplified no I tell as I say you please confuse do not confuse between DC and AC AC signals will get all other frequency components DC signal cannot get it will just saturate a 1 DC value on the plus side or the minus side is that clear clear to you if I have a only DC inputs either it will go to VDD at the output or VSS okay but if I AC signal over reading a bias voltage then that AC signal in the non saturation region you see understand how do I write non saturation a 0 plus a 1 X plus a 2 X square you write the by expansion series X square term means sin square omega t sin square omega t means to sin omega t minus 1 so 2 omega d term appeared you take the cube will get 3 omega d terms so you can see when small signal AC goes it will give harmonics DC does exactly it will give us fixed value of 2 DC value that is what comparator does it actually fixes it to fix 2 values so it will enhance by that much gain whatever DC value input you have into the gain that is the DV 0 by DV in which is your gain multiplied by the DC input that is the output voltage so it will not because in those region there is no signal okay the device is not introducing any harmonics from itself the device gives you non harmonic content because in non linear relationship the term square cube 4 terms occurring and that only when you are sin omega t as signal then sin square omega t sin cube omega t they will give 2 omega t 3 omega t and combination of these are the signals okay so only AC is give you this kind of okay we looked into yesterday that a differential amplifier can be in the MOS differential amplifier or it can be BJT I will not do be I may be at the end of this if I am I may just show you a bipolar BJ defam I may solve something the similar thing has happened in MOS but other things you read in the book which I officially said Cedr Smith and me okay so read there the other parts of bipolar okay I will only do MOS parts and will expect you that you read bipolar okay if you have an issue that okay it is not same and it is not correctly coming and you do not understand that part we may do again in the class otherwise we assume that techniques are same and therefore can be applied to any other blocks as well okay so we said we define 2 signals if V in 1 and V in 2 are my inputs to a differential amplifier which has 2 input ended signal it is not single ended the 2 inputs then we define signals as V ID which is subtraction of the V in 1 and V in 2 whereas there is another signal we call common mode which is the average of the 2 V in 1 plus V in 2 by 2 now as I said yesterday the fam has the advantage that same noise normally is common mode what does it mean on the board terminal noise has same sense okay or same amplitudes and the defam has the biggest advantage that it rejects common mode signals that means anything which is common output does not show that is that clear so if there is a noise over reading on your signal and if it is common mode which will should have been normally will occur then the output will not show noise amplification is that clear that is the advantage why defams are opams are used because it rejects other signals which is common mode and the word there we use is what common mode rejection ratio how much it can reject is the criteria of a good opam large CMRR should be good but this word she will come back and say no one do not go 125 dB a CMRR or 200 dB CMRR because if that happens something else will be hurt heavily your bandwidth may not be there phase will not be occurring so there are issues but larger the CMRR larger is the better is the circuit for operational or defams okay so I will take minimum defam CMRR should be around 80 to 85 dB should exceed a not more than 120 dB but around that 120 is okay I am not saying it is bad but never try for CMRR of 200 okay in fact the theoretically the CMRR may come as infinite how much theoretically ideal situation CMRR is infinite okay but there is nothing ideal in the world so is CMRR is never infinite in the world okay so you see why that does not occur okay so this is just what we did just the other day okay we said a defam has two single ended amplifier in which their sources are connected and there are two resistances there are two single ended amplifiers assume Rd1 is equal to RD2 equal to RD then this is the circuit which we called the differential amplifier or defam in short diff am okay this ISS is the biasing current is in mass it is normally called ISS in bipolar they call it ICC or just I okay so if you are doing otherwise just look they only may cause capital I that is it VSS is the negative supply so opiants with always are having dual rail power supply what in my dual rail plus VDD and minus VSS but there are single rail opiants also available that is only VDD is that clear I am not trying to say that single rail opiants are bad or worse of course bad they are worse than dual rail power supply based opiants okay this has I repeat again has anyone started looking why negative voltage are relevant in analog whereas in digital I will never look for it think of it what is the advantage I get difference why still am VDD minus VSS minus way that is the net voltage if it is 2.5 2.5 it is 5 volts so I could as well put 5 volts single supply if I have 5 volts supply I can make 2.5 minus 2.5 which is also 5 or I make 5 0 but why I do 2.5 minus 2 and normally we also see that the same opposite is occurring 2.5 minus 2.5 not 3 and minus 2 okay that also has some disadvantage so think of it maybe at the end of opiants I will say why dual rails dual rails are very relevant okay some partial answers I gave someone who asked me here but I will give them more detail later let us say the first case defam please remember I again show this v in 1 v in 2 are the 2 inputs and the common mode is v in 1 plus v in 2 by 2 difference signals is v in 1 minus v in 2 okay let us say defam has same inputs at the both end v in 1 and v in 2 is that how much is difference 0 but what is the common mode v in plus v in by 2 means v in is that correct v in 1 plus v in 2 if they are equal that means at both side the signals are same v in okay so v in 1 is equal to v in 2 and since they are connected at the gates vg1 and that is equal to vg2 is that correct this is the common mode part in that now you can see from here in our circuit can I show you little bit the source of both call it m1 m2 for future source of this both transistors are connected common they are same so what will be the potential on both side will be different or same same because at a at any node there can be only single voltage that voltage I call vs source voltage is that correct so how much is vgs for this v in 1 minus vs how much is this v in 2 minus vs is the vgs for m2 but since v in 1 is equal to v in 2 and call it v in both transistors have same vgs is that correct if they are same devices of same threshold vgs minus vt is also same let us say iss is so balanced that they give sufficient current so that both devices remain in saturation so what is that means this current half will come here half will come here because both are vgs minus vt is same for both devices is that correct because if they are equal pts are same the half of current must flow through them that is exactly what she said yes we do not apply it comes if I apply v in 1 v in 2 there will be a possibility that they may be equal at a point is that clear so common mode is a not necessarily of course noise is essentially is a common mode signal is it not okay I show you the game there how do we given a different signal it can always be represented some of common mode and difference mode okay okay so we say vg1 is equal to vg2 is equal to vgs1 equal to vgs2 and we define vcm as v in 1 into vgs1 vgs2 and the source voltage is of course vgs vcm minus vgs what is why to say sorry not vgs actually it is vg vg minus vs is the signal there vgs so we say vcm is source voltage is vgs minus vt is that correct vgs minus vt is the drop across that is we defined as bov vgs minus vt we defined as bov so we substitute this is vgs1 is equal to vgs2 one can always say that id1 plus id2 are equal if they are half-half situation if they are equal but even if they are not equal the issue now please take it here they are equal is that correct even if v in 1 is not same as v in 2 one may have a larger current than the other but the net current will be how much the is because that is what you fixed so sum of id1 plus id2 will always be equal to iss if they are equal so which each will be iss by 2 if not equal one will have a larger value than the other this is what defam allows okay if they are equal half-half if they are not equal one will draw larger other will be drawing smaller but some total will only come to iss independently this is exactly what we are looking into okay vg minus vs is vgs but vs is common to both okay so is that clear to you because the subtraction is same for both is that correct same because vs is common voltage okay so if I do that if id1 is equal to id2 it is iss by 2 but we know the current in the this is half beta n dash w by L by 2 vgs minus vt square iss is then represent as a v o v square so v o v is 2 iss upon beta n dash by w by L at what point but where is this defined when the current is half-half in both circuits is that clear id1 is iss by 2 and id2 is also iss by 2 for this condition v o v has been defined normally we do not define that way we define only normal but in this case for the common mode id1 is equal to id2 and at that condition the v o v is defined by 2 iss upon beta n dash into w by L okay for a max a square there is a square there is a yeah okay this half this is half beta w is w by L but the current essentially this is iss please remember what is iss if one of the device is working it is beta n dash by 2 vgs minus vt square if it is half current half the current will go to iss by 2 on one side iss by the other side I agree what you are saying I fully appreciate but okay call it like this to say that okay if one of the device is operating normally we define that my view one of the transistors since it is half the current for individual cases when equal currents are there we now define a new v o v which is related to half currents iss cut the full of formula and for that we define new that is for single transistor with one drive completely driven by it but since it will be half half then I say for that half we define new v o v this is it I agree we need not have defined we should have kept normal v o v also to come additional two terms somewhere there fair enough nothing goes wrong is that clear it is only a normal nature which said Rasmith has been using and I thought since you are going to read that book I should follow their normal nature otherwise I myself would not have done it I agree with you what we are she is saying this for why this half is coming here this half is essentially this is a normal ideas current for any transistor so I say if only ISS is flowing in one transistor half beta into VGS minus VT should have been the current is that correct but since each is driving only ISS by 2 I am just dividing it by half both sides no that is what I am I am saying you know when one transistor works if that is what say the definition was something like this that if only one of the two transistor works the other does not all the current will flow through one and that I call half beta and dash W by L into VGS minus VT square whatever VGS for that transistor is that clear to you that is the current it will flow now you say if it is half half then the VG is equal still equal okay but the current is now shifted half half so I divide the current by half whole one whatever we use other either other okay we will come back to you modify the other sector do not worry this is what they have done it I normally I would have agreed I would not have done it but since they are following this method I thought I should give you their method okay you are perfectly justified so what is VD now can you tell me VD okay so what is the drop at the drain the resistive drop ID 10 to R is the VDD minus that should be the output voltage so VD 1 is equal to VD 2 equal to VO 1 equal to VO 2 is VDD minus ISS by by 2 times RD if RDs are equal otherwise they may also not be seen then what is the output subtract subtraction of VO 1 and VO 2 0 if they are 0 what do you expect the gain if the output which is defined by me as VO 1 minus VO 2 and input is how much common mode V in equal to V in 1 equal to V in 2 so what is the common mode gain what is the common mode gain output voltage divided by common mode signal output voltage is how much 0 VO 1 minus VO 2 is 0 so the common mode gain is 0 in the case of differential amplifier that is what the rejection word is clear to you that any signal which is common will not get amplified at the output if the difference of output is collected is that clear if the difference is collected VO 1 minus VO 2 there is no gain for the common mode signals now question is this valid statement because it is not true because the way we will define later which we just now said word CMRR is essentially called ADM difference gain upon common mode gain okay so what is CMRR for this infinite and I will say ideally that means this condition which I put is an ideal condition ACM is 0 is an ideal condition why does not occur as 0 and how much it will occur will go and truly evaluate the ACM is that no it is not too for it is equal in common mode the signals are same V in 1 is equal to V in 2 is only common mode correct so they correct if the two signals have a component which is difference possible they will get amplified but the common will reject itself yeah but we already said we will always operate in a linear mode that is what I day 1 I started with you when I showed you that I am always going to stick in this is that clear and that condition is still valid if you are doubt is doubt so let us clear the doubt if this is for any transistor this is my VG and this is my VS if this is my VG and this is my VS so what is VGS for do VG 2-VS is VGS 2 VGS so VG 1-VS is VGS 1 if VGS 1 is VG 1 is equal to VG 2 VGS 1 it must be equal to VGS 2 that is what I said yeah that that is because the difference between the two is same what I said it is okay oh sorry I made a mistake you I should write VG mind VG 1-VG 2 is always equal to VGS 1-VG yeah yeah I agree with you yeah your point of view what I said maybe around what I essentially saying what she is saying is that the difference is equal VGS is equal to VGS yeah you are right the idea of that VS since it is common this it will also get as it close to 0 the reason why I said for AC this potential will go to 0 so that is for that AC part yes they are equal for DC they are not you are right yeah you are right VGS 1 is equal to VGS 2 okay perfectly justified okay normally our assumption in this that all transistors are identical all resistances are identical and the current source is ideal current source please take these three conditions in deriving this thing we made three possible this one is the two transistors are fully identical the W balls are equal the thresholds are equal okay second condition we say the IDs are exactly equal and third condition say the current biasing current source is ideal is that current if there is a resistance there they may have some issues okay three conditions are called ideal conditions under that state yes the common mode gain will be infinite infinite or cause or is 0 and therefore CMRR will become infinite please take three condition is that clear three conditions okay I should say third one also and ISS is ideal current source I will come to this very soon and I will show why I said otherwise the current in both VO 1 VO 2 will be different for both even if the currents are same so so essentially VO 1- VO 2 will never be 0 then even for half currents if I do they are not equal then the drop across them are not equal so the subtraction will not be 0 so if that is what I say since they are not equal that means there will be some difference voltage so common mode will not go to 0 there will be some finite value is that clear VO 1- VO 2 will not become 0 then it will have some value which will be smaller because I already 1 already 2 even if they are not equal they may not be 2 for 1 10k 100k 10.05k 10.02k that is because of the process which we transistors are made one cannot guarantee but how do we say we guarantee on these circuits why did I say in integrate circuits this is doable discreet nothing is doable is that correct in discreet I can never guarantee RD1 equal to RD2 Kithna be sold registers like out since most of the meter given to you to monitor is you are only using oh meter who is called least count is not come a jada hack key 10.0 ke aga kuchwo karakne dein is at that so you always will both are 10 okay essentially if you have a good measurement system you will find they are not equal and if they are not equal even with everything else VT equal possibly VT will not be equal for two transistors okay so in which case what is going to happen is V1- V2 will be some finite quantity which means ACM will be some finite small quantity but finite quantity ideally it should go to 0 and therefore CMRR rejection should be almost infinite okay. However is this number is what we are going to see as I say how much I said you please remember this is range you must work in real circuits 80 to 120 DB may be CMRR hosha ye ushe bawa kia to kya hoga hoshe kum kia to kya hoga ye switch in like is that okay these numbers are only for those who are someday going to work on integrate circuits designs for this these numbers are crucial okay okay there are two these are two I am just this is not the ideal way I am explaining but just there is another term which all opium people use they call input common mode range what they called it ICMR and this is essentially coming from the diffam itself so shown here is that what we are input common mode range so what does that mean in your mind without seeing this what does that I mean input common mode range so what is the maximum and minimum common mode voltage which are possible which will allow device to operate and saturation both transfer to remain in saturation and in linear mode is that correct if that occurs we say this is the maximum VCM and another is minimum VCM you must work within this so what does that mean if the noise over this value then it will show you at the output as well is that clear so there is a limited range in which VCM can be operated okay here is some tricks on that general method may have to betaditao a skill in a whole a circuit wallo ke liye hai whenever I want to get a maximum value which is occurring at the input you always go from VDD you calculate from VDD down is that correct whenever I want the minimum value you should always calculate from ground or minus VSS towards the input is that point clear these two terminal edges you take independent of this which I am going to use I repeat for the maximum value you come from this for the minimum value you come from this whenever any maximum values that input or you are trying to see for maximum start from power supply and for the minimum start from minus VSS either say a KITMA or either say that means maximum value is decided by VDS of this and RD of this minimum value is decided by this as well as the VDS is that clear so these two values are different from each other and one gives max other gives minimum this is true for this circuit true for any circuit in which such calculations are to be performed is that correct I repeat for the max start from higher end to the point where you want and for the minimum go from the lowest end to the point where you want to come this is the standard method which should go here independent of what I am going to teach now okay these I keep saying you because you should know the way tricks we follow later okay so we say VCM occurs when M1 and 2 are the age of saturation when both transistor are at the age of saturation we say that is VGS minus VT is equal to VDS so we say what is common mode at the great source voltage okay so VC max minus VT is equal to VDD minus ISS RD half the current both transistor on half of VC maximum minus VT is equal to V is that current what is this value again see the circuit I just now said VDD minus this drop you are here at the drain please look at it VDD minus this drop you are at this end then you want actually VGD what do you want to reach here you need a VGD but if you say VGS minus VT equal to VDS I can get VGD which is VT is that clear so I can get this into VT plus VT as I repeat if this is at the saturation I am now saying okay that expression anyway I am showing you VC max minus VT is equal to VDS okay at that point it is at the age of saturation VGS minus VT is equal to VDS is the age of saturation so if I substitute this and that voltage must be equal to VDS which is VDD minus this this so if I equate them then I get VC max is VT VT plus VDD minus ISS by 2 into RD is that correct this is the maximum input common mode possible what is the condition it is it will if you go beyond that this condition will get violated is that correct device will enter which region linear region and then your whole linearity will be lost is that correct is that point clear so that condition which I put is that device should remain in saturation but the maximum will come when it is at the age of saturation is that correct so that is the condition now coming to the minimum side from where I should take minimum from the source side the minimum occurs such that VS which is the source voltage please remember source voltage is a source voltage is current source how do I make a current source if I use a transistor put a proper VGS this and I see to it that the current is constant here okay that clear then it becomes a and what is the other property of a current source not that the only current is constant or source is close to infinite okay that is the condition of a good current source so there is a voltage drop across this transistor VDS of the current source so this VS is essentially VS-VSS is how much the VDS of the current source that name I have given as VCM VCS what is VCS is the current source voltage drop current source not ideally what should be the voltage drop 0 okay but it is not ideal so it should be some drop across the VDS which is the VDS of that transfer is the VCS number I gave you so the VDS for the current source is VS-VSS please take it this is minus of minus that means it adds in fact is that correct VS-of minus means actually that voltage is adding to that is offset plus value it will give so the VC minimum then is okay first you remove this VTS this it is this VG please take it this voltage please take it what I am saying the minimum value is VGS plus VCS is that correct is that clear this value plus this value is the input is that correct so if I do that I write VC minimum is VGS plus VCS my VCS minus V which is equal to minus VC just now I wrote common source voltage VDS for that so we say and I added VT and subtracted VD why did I do that just to make it some VOV term appearing there okay actually this VT was not there but I just added and subtracted so I get VOV plus VT plus VCS plus VSS okay is why it is a minus VSS but it will become plus why VSS is negative quantity so this is called VC minimum so what is the input common mode range then what is range called maximum minus minimum is that correct what is the range max minus min so VC max minus VC min is the input common mode range what are the two conditions it is satisfying one is devices at the age of saturate it goes at best to the age of saturation for maximum input signal to allow in common mode okay and it goes to the minimum of that value when the current source is a constant current source anything violated there will not allow that VDS to remain in saturation which means the device will then it will not give a constant current is that correct that means the bias point will shift away is that clear and therefore these are the two swings voltages in which common mode signals are possible to be amplified the current source will not act like a current source because that VDS will be then smaller than VGS minus VT for that current source the device will enter linear mode so it will act like a resistor there and very small register if it is large register there is no problem because it is still a constant current it becomes smaller register that is the issue and then we will say CMRR will go to 10 dB okay that is what current source is not coming from somewhere else it is a part of the defend actually and the way it will create it I just showed you how will I going to create that okay there will be a transistor sitting there okay is that okay okay so having shown you so ICMR is VC max minus VC min so you that is the range in which so many times when I design an open one of the space they give me this is the ICMR okay this is the ICMR so I actually from there I know what values I have now value I can get out so that the ICMR is within the range given to me so they may give minus 2 to plus 2 or plus 3 okay so I must now work within this range so at no time the device W bias and the currents are used should go beyond these values to make device going out of this range is that clear that is something one has to design we take care of ICMR day one because that is the limit I always see okay okay the current source must remain current source that means it must saturate but that is always because that I says if it comes out of it will not as long as that current is constant that device is in saturation anyway even at the age of this ISS is still flowing that will still ISS by 2 will still make M1 a saturated but that as soon as this is condition that will automatically get satisfied we chose ISS such that M1 M2 gets satisfied half the current will make both saturate as long as you are on the age you are still satisfying the upper condition if you get out of that that the current source does not remain same current or much smaller than both will come out of saturation anyway not only this the upper one will also and that is why I say we say input it will come out of it okay so device will not in the linear mode anyway is that okay okay to some extent yes okay when I design a current source I know that voltage what the videos I am using okay is that clear this will be close to VT okay so we say VT plus some plus some as we call okay so we know that yeah so best current source will be videos larger than that so at the age it will be VDS minus VT is videos so we say VT so if VT drop head difference VGS minus VDS may put less saturation per head that is the criteria so is that okay analog circuits are only 10 to 20% of any mixed signal chip which you use like wireless mobile or any other but if that 10 to 20% circuit does not work well you are 80 to 90% digital will fail immediately because yeah he is up the front end a all analog blocks are at the front end if things go wrong a deal for everything is out anyway so I ask is that which be some I this act I am I be some I this act so remember it is like saying this is the people who control everything in the world right now okay okay so we have seen common mode so let us look for the major worry major interest for us is the difference mode common mode is very small we are only trying to reject common mode signals fine but amplifier is not for rejection amplifier is for amplification so let us see what amplifications we get and that is our major interest so we do the same if I am once again shown here if I say I have a different signal of V in 1 minus V in 2 that is our difference signal to input signal cut difference you have a difference signal V in 1 minus V in 2 depending on the V in 1 is higher we had is plus if in one is smaller we had is negative fair enough but otherwise difference is always there so I now play a game I say I apply a V ID by 2 here and I apply a minus V ID by 2 the other side so how much is the difference signal V ID is that clear so when I say V ID alternatively I can also assume that the one of them is grounded and this input is V ID so V ID minus 0 is still V ID so there is a single input the other input this is what open is doing and why I am showing you is this okay we recollect that first circuit which I showed you in most cases this is grounded one of the terminal is grounded and you give input only at the other end this condition is exactly what I am showing one input is given here the other input is grounded so automatically input signal become different signals this is what you actually do in op-amps equivalently saying this is what we are doing in a different is that correct I appreciate I agree with you any day you do yeah say yeah I could voltage measure curve yeah say yeah voltage measure curve very much a different signal in a time is a V ID irrespective whatever we do the DC biasing is not controlled by this this is biasing is only controlled through ISS I am not worried about the status of M1 and M2 so I am only interested to see V1 minus V2 divided by V1 minus V2 I never said anything more than that it does not as long as you take a different signal here how does it matter we are also taking a difference of V1 minus V2 you got the point in respect to whatever I do here this will be different in two cases as you are saying but the difference should be will come same that is what we are trying to say this is what superposition is trying to say chilly now okay you wait for this I show you this is called when the superposition is possible this is called half circuit analysis circuit which I shown you is called half circuit analysis and when this is valid we will explain you when this is valid if this potential is constant this half circuit analysis is valid there is a theorem for it okay what you are questioning can be proved that this writing equivalent of half by 2 is equivalent of saying VID and that is why is the difference in the output voltage will correspond into the values here and here so they change so if these change the difference will as long as you are in linear the difference will remain same independently that is exactly what I am saying what you are asking is what I am saying it will always this lower will change this this higher will change this the difference will be as much as saying one goes up the other goes down if this goes up this goes down so difference is same as that condition I keep saying linear as long as they are in linear situation this will occur like this if this is going higher this will go low this is equal to equal to 0 that is that will come like this is that clear so our assumption is not if I say equal means what what condition I am saying equal means common word yeah output is 0 is that point clear in common mode both side VID by 2 yes V1 minus V2 is 0 otherwise one is higher other is lower all other way depends on the sign is that clear so essentially we are saying this is always valid as long as this voltage is constant will prove this point called half circuit analysis oh sorry everywhere please now in onwards never ask me okay I am very sorry if I do not write this you do not ask me unless I said it is single real you assume everywhere do okay is that point clear what is the difference signal we are looking at what she is questioning is very good but she what I am saying any if do not take half minus half half minus half then one of them will conduct heavily other will be smaller as they change you change the polarity still it will be opposite way it will move okay so difference at the output will remain same independent way how input goes the way input goes so if the output will shift correspond okay and condition is linearity is maintained okay okay by now logic VID is equal to VGS 1 minus VGS 2 because source is common okay what is VID VGS 1 minus V1 minus V2 so which is VGS 1 minus VGS 2 if VID is positive what does that mean VGS is your code is are now coming your answers are now coming if VID is positive VGS 1 is larger than VGS 2 if we add is negative VGS 2 is larger than VGS 1 okay in the first case IDS 1 will be larger than IDS 2 in the next case IDS 2 will be larger than IDS 1 okay. So whichever has larger VGS will pull more current whichever has a smaller VGS will pull less current so it can also occur for a given value of VID the other transistor may switch off is that one if I change VID this other is opposite of that so that becomes smaller so that turns on the switch off one of them all the current will be drawn by only one side is that clear if I change VID from say minus to plus one of the transistor may actually go high draw start drawing higher and higher current the other will start reducing at a given VID the device the other side may become off all of the current will be picked up by the higher VGS 1 okay all of it that means when VGS 2 goes less than VT that transistor will be switched off whichever VGS goes less than VT that transistor will switch off then the one which has larger VGS will draw all the current is that clear all the current so we may say whichever is fully on transistor it will draw all ID in the let us say in the case I VID was such that ID VGS 1 is greater than VGS 2 and we had is increasing VGS 2 is going down so in that case IDS 2 is 0 and IDS 1 is equal to ISS all the ISS is now flowing in that transistor is that okay all of it is going to one arm okay what is the condition I am using all the circuit please remember if I add lambda here 1 plus lambda VDS what will happen this equation will become non-linear okay and then I will have to really do on the spice only and not analytically I am not adding those terms because otherwise solving numerically is the only possibility is that clear so in when the problem you will solve in the tutorial which I am now giving next time you will you first learn spice and then that time lambda need not be 0 in fact you do this analysis put lambda 0 and put lambda 0 1 or 0 2 and see what difference it give it will give the literally sufficient difference and that is one of our worries also okay is that point clear if I change VID such that one VGS 1 start increasing VGS 2 small then VGS 2 may go below VT M2 transfer may switch off all M1 will draw full current ISS or vice versa can open if I make VID minus larger then we say M2 will take all the current and M1 will become switched off okay this is yes okay so there will be some maximum minimum VID in which one of the transistor will draw full current is that correct so let us wait for that expression one can see from here sorry if VID minimum becomes equal to minus 2 root Vov VGS minus VT we may say the trans let us say this is IDS 1 and this is IDS 2 maybe I should write this this is IDS 2 sorry maybe IDS 1 this is ID sorry IDS 2 so in minus M2 turns on okay and in plus M1 turns on so if 0 say ISS jayga 2 ISSA 0 ketra where they will meet which point ISS by 2 point they will both VID by 2 and minus VID by 2 parvo dono a 2 3k equal is that clear this essentially saying except for these ranges currents are not linear is that correct currents are not linear except for these ranges so root 2 Vov minus 2 plus root 2 Vov may he input signal will be Raha VID Raha then only amplification in linear mode is linear linearity is possible so the limit of input for even different signal is there is that point clear earlier concept I am in a common mode of many different mode will be able to keep in between these two only values there is a linearity and actually you should not come even closer to this why because if you come closer here there is no linearity so actually it should be less than that both side is that clear is that punk you are at this curve they are not linear so actually it should be away from the H points what does that trying to tell you again small signal attitude Aga has made do you get the point if VID becomes larger then what will happen only one transistor will operate and it will go into a saturation value either minus R plus is that clear so to remain both transistor in linear system you should not exceed VID within this more than these two ranges what does that mean VID should be small values so again difference amplifiers can only amplify if input say different signals are small enough is that correct. Because I have not shown you properly this slope is very high what is the typical slope of this lines you know is the value of gains open ended gains is 10 to power 4 and above so if you let us take a case I have 1 mv signal so how much will be output 10 volts is that correct 10 volt if I have a minus 1 I have minus 10 volt but power supply the punch or punchy high the best design is that correct so even 1 mv difference signal may not be allowed if the gains are very high in the open ended system that means no feedbacks normal defam cannot take larger difference signals is that correct because the gains slope of these curves are very very sharp 10 to power 4 10 power 5 that is what we design in fact so where do you think the larger gain will help you in the case of which circuit reaches faster to plus VDD or minus VSS what is the circuit should be called fast comparator is that correct small change output went to VDD or minus VSS so output I immediately came you came to know whether it is plus or minus so I compared the signal as fast as possible is that point clear if the slopes are very steep the gains are very high 10 by that value gain requires a very small change at the input okay so if I say V in 1 is 0 or V into 0 and V in 1 is what I am trying to say is this which is interesting again you should know what I do in the normal case let us say this is my V in 1 and V into is grounded so if my input is something like this AC signal as this crosses 0 let us say this 0 it will show minus value if this crosses minus and so plus value instantaneously instantaneously finite time some nanosecond to microsecond okay so faster the switch will occur when so even with a small change over 0 it can show you an output going to 1 or 0 in some sense is that correct such are called fast comparators okay so car condition will be fast comparator key key they should have very high linear gains okay why high linear gain of gains how do we increase the gains okay if I am the gain 10 power 4 or 5 okay so in dono milke or even there is a buffer does not have a gain function buffer is only going either to 0 or to 1 that means drive higher side or lower side will show what is buffer otherwise this is how the gains will be very very high is that correct very very high and that is exactly where op-amps are used in such analog to digital applications is that clear why I am showing all this because most of the circuit did I what did I say they will be digital your inputs may come analog so I want to give them outputs okay yellow may what I have there where such circuits will be useful okay next time first thing we will do just we will first look into large signal operation what does that mean larger signals and then we will say what is the difficulty when I get a larger signal and then how much smaller signal I should get so that the thing which I said I will first do a large signal analysis and then we say okay what is it creating so okay reduce your signal to this value for good amplifiers is that okay so you next time start with large signal amplifiers please start reading into said Rasmith which chapter I do not know there are they close on time mass FET amplifiers is a separate chapter or bipolar I do not know I have not seen recently but maybe in the same maybe in the same just look for this today's work and we will start with large signal and finally we will give you defend is that clear. Is that clear. Is that clear. Is that clear. Is that clear. Is that clear. Actually yeah you have a point essentially it is a small V OV is DC plus AC so DC the fixed T you got the point that OV may OV are capitals okay essentially saying it is AC plus DC so DC value is the fixed T bias so you run.