 Hello and welcome to this presentation of the STM32MP1 USB full-speed and high-speed interfaces. It covers all the features of these interfaces, which are widely used to connect either a PC or a USB device to the microcontroller. This figure shows the connections between an STM32MP1 microcontroller and a USB connector. The STM32MP1 features a USB high-speed communication interface, allowing the microcontroller to communicate typically with a PC or a USB storage device. The simplest implementation is a USB peripheral device, but the STM32MP1 microcontroller also supports the USB on-the-go functionality. The above diagram connects the high-speed pins, but the full-speed pins can also be used when both high-speed ports are used for USB host ports. See other module, USB-H. Let's look at some of the key features of this USB high-speed interface, which is a USB specification 2.0 compliant interface that operates at a 480 megabits per second bit rate. In the simplest form, a USB FS device can be implemented. Built-in support for link power management adds enhanced power modes on top of the USB 2.0 specification. In addition, the on-the-go or OTG functionality enables implementation of an OTG product or an embedded host, both of which have the capacity to behave as a targeted host. The battery charger detection function allows for increased current to be drawn from BC 1.2 compliant chargers up to 1.5 amps. USB 2.0 high-speed is also available via the ULPI interface. The same modes of operation are possible when coupling with an external ULPI transceiver. In this block diagram, the USB OTG high-speed controller core is shown in the center with its data FIFOs below. It can either be used in conjunction with the second port of the HS or high-speed PHY or the FS or full-speed PHY. These PHYs on its right side handle the analog signal levels, including many specific level detections relating to on-the-go and battery charger detection functions. The USB interrupt goes to the Cortex-M4 processor to signal various USB events. The AHB slave interface enables read-write access of the controller registers and the power and clock control block. Transfers to and from memory are handled by a DMA engine inside the controller via the AHB master interface. At any given time, one of the two operating modes will be functional. Peripheral mode, which will be used for a regular device or an OTG device when operating in peripheral mode. Or targeted host mode, which will be used for an embedded host or an OTG device when operating in host mode. Interrupts from this USB block can be triggered by a large number of events or state changes. This slide and the following three slides show all the events that can trigger an interrupt. As can be seen, these interrupt sources are diverse. They range from events related to low power management and OTG to events related to normal host behavior and regular USB reset and disconnect events. In this second slide showing interrupts, another diverse set of sources is described. OTG functions and FIFO status events are listed, as well as a general register access error. Low power modes for the high speed core are available when USB suspend is active in device mode. Refer also to the next slide. The USB OTG peripheral is fully active in run mode. During USB suspend, sleep, stop and LP stop modes may be used. Within the USB module, certain dedicated bits are implemented to allow debug functionality in a USB application. They relate to FIFO status and contents and the scheduling of periodic queues in host mode. Additional details of these debug bits are listed in this table. USB PHYC is a small controller needed whenever the high speed PHY will be used. It is to be used for controlling the PLL inside the high speed PHY and enabling OTG controller access to its second port. Fine tuning of the high speed PHY should also be done by using USB PHYC. This is necessary to get notably a well adjusted eye diagram. Here is an application example of a USB OTG or on the go application. Power can be drawn directly from the USB VBUS signal when in device mode. The VBUS should be generated locally when in host mode. A single crystal oscillator, for example 24 MHz, is needed outside. For complete USB specification documents, please refer to usb.org. The USB 2.0 document homepage has a zip file containing the USB 2.0 and OTG 2.0 specifications and an ECN for LPM. Please also refer to the MPU wiki pages.