 Hello everyone welcome to the course advanced logic synthesis first of all let me introduce myself my name is Dheeraj Taneja I work for for Broadcom Technologies Hyderabad I have been working in this industry for past 11 years now I did my graduation from Bits pilani in 2002 in electronics engineering let us first see what what all we would study in this course the objective of this course is to study the components of digital design that is the gates various sorts of combination and sequential gates that that make up the digital design and then learn the process of converting the the higher level design which is written in an HDL like where a logger VHDL into the gates using the process is called synthesis so we will see the basic we will start with basics of synthesis and go on to see the advance concepts of synthesis so this course is divided into five major units unit one and unit two are carried over from the course VLSI design so they are more or less refresher course into the MOS transistor how the what is the what are the transfer characteristics of T MOS and N MOS how they are combined into a CMOS and how the gates are built using CMOS we will see basics of layout we will see stick diagrams which are the representation of layout then unit two we will see we will study about the different logic families that make up the digital design like N MOS logic ratio logic pseudo and MOS transmission gates and so on we will also look at how do we calculate the propagation delay or how do we estimate the propagation delay of a cell we will see different kind of combination and sequential logics logic design techniques then unit three onwards we would look into the process of synthesis we look into what are libraries what are different kind of views how do we we will also see how do we write RTL code and what construct what construct of RTL corresponds to whatever what part of the digital design then we will see how to we will see the whole process of synthesis unit four we will see we will visit some advanced techniques of synthesis let us say you are not meeting a design constraints what else could we do what more can we do in synthesis to make sure that our design needs the performance goals unit five is a very interesting topic called timing analysis this is the this is a technique which is employed industry wise to make sure that the design meets the performance requirements of a particular technology note the the course out at the end of this course a participant should be able to write a basic RTL code and synthesize it by setting constraints by you should be able to validate the results and analyze the different synthesis reports you should be able to synthesize a design which has some targets like area and timing you should be able to perform critical path synthesis if required and then lastly you should be able to perform timing analysis on the synthesized netlist the if time permits we will also look at the functional equivalence which this is the process by which we make sure that the netlist the gate level netlist that we get out of synthesis actually is functionally equivalent to the RTL so this makes sure that whatever commands we give to the tool have the desired effect the we will go back to the slides and the references for this course are first of all we will use this is an officer recommended course material and lectures we will use a design compiler and time-time user guide for units 3 4 and 5 then there are couple of books which you can refer to one the most famous one of which is digital design by Morris Mano and then there is a book of fundamental of digital circuits by Ian and the unit 1 and 2 lecture slides are derived from the VLSI design lecture slides which are prepared by Professor David Harris and they are available at this link they are they are freely available for download I would recommend each one of you to download this course material it is a very useful course material for VLSI design then the tentative course plan is this the number of hours I plan to spend on each unit so as you can see the unit 1 and 2 combine is when unit 3 4 and 5 is the majority of the course which is expected since unit 1 and 2 are more of a pressure material we should be focusing a lot more on synthesis and timing analysis that is why unit 3 and 5 are heavily loaded a unit 3 4 and 5 also have lab lab work involved since a lot of it is should be practical in nature the theories a minimal part let us start with unit 1 unit 1 we will assume that everybody is familiar with the basic working of MOS transistor but unit 1 we will again go back to most master and see and just visit how see how it works mostly what we are concerned about is how a MOS transistor works as a switch since that is the functionality we use most in the digital design so we are looking at integrated circuits which means there are many many transistors on a on one chip very large scale integration means in today's world it means billions of transistors on a single chip the most popular technique for manufacturing VLSI design circuits is complementary metal oxide semiconductor which is in short form it is called CMOS why is it most popular is because it is fast it is cheap and it is it has low power there obviously there are circuit circuits which are faster than CMOS there are also circuits which have low power than lower power than CMOS but when we combine the all the three characteristics that is the speed the cost of manufacturing and the power in all three when combined together CMOS scores heavily that is why it is most popular nowadays we will see how to build our own CMOS chip that is in first part we will see how CMOS is used to manufacture gates different kind of gates we look very briefly into transistor layout we will not look into fabrication in this course we look the layouts are not not very very big part of this course we will just see the basics how how do we how how does the layout look like what information does it convey and we look briefly into stick diagrams which is a paper way of doing doing layouts the tools do not the stick diagrams are not used in packed tools but for our own sake when we want to represent a layout on paper then rest of the course we see that how to build a good CMOS chip using the process of synthesis and timing analysis let us begin with let us have a quick look at the silicon lattice silicon is the most popular material for real estate designs the transistors are grown out of a silicon substrate by method of deposition and etching silicon being a group form material is a is closely is forms of closely bonded crystal lattice with four of its immediate neighbors the silicon if you see the diagram the each silicon molecule is bonded to four nearest silicon molecules silicon atoms to form a form of crystal lattice silicon it is neither a conductor nor an insulator it is a semiconductor your silicon does not have any carriers because all the four bonds are satisfied there are no free electrons available it is a very poor conductor the the prop we group 3 or group 5 elements are added to silicon to increase the conductivity these are called dopants dopants a dopant is nothing but an impurity added to silicon to increase its conductivity when a group 5 element like phosphorus or boron is added to silicon that it contributes an extra electron per atom and correspondingly the free electrons are available and the conductivity increases this type of material is called n-type silicon if on the other hand if group 3 element is added to silicon is doped there is a deficiency of electron which is called a hole this type of material is called p-type the most fundamental the most basic circuit that can be built out of a p-type and n-type device is a diode a diode is a junction between a p-type and n-type semiconductor the current flows only in one direction so on the n-type there are there is an excess of electrons on the p-type there is an excess of holes the electrons flow from n to p therefore the current the conventional currents flows from p to n so p acts as an anode and n-type acts as a cathode so the important point to I am sure everybody knows it but the thing to remember here is that the current can only flow in one direction from the p to n-type now the extension of a diode is a transistor now a transistor is is made up of four terminals gate source drain and body many times in textbooks or in many times you would see in the matter that discusses transistor many times the body terminal is usually not discussed but in in terms of when we talk about fabrication or when we talk about the CMOS gates this body becomes a very important terminal so let us see how how nMOS looks like so there is a n plus these and this n plus means that this is a heavily doped n region on a substrate which is a p-type material a plus sign usually it denotes that the region is heavily doped for example this is the notation here says p there is no plus sign so that means it is likely doped compared to the n plus region the two terminals called source and drain which connect to the heavily doped n plus region in case of MOS transistors the the source and drains are interchangeable you can use anything for source and anything for drain then there is a a strip of insulator which is silicon dioxide and over silicon dioxide a strip of polysilicon or or a metal right now the most popular technique is depositing polysilicon so this this acts as one more terminal called gate so if you see that the body of the body of the device that is a substrate and gate are conductors silicon dioxide is the insulator that is why it is called metal oxide semiconductor although the gate is no longer in today's technology the gate is no longer made of made of metal it is made of polysilicon which is a variety of silicon that is a very good conductor just like a copper metal let us see the operation of the nMOS transistor so usually the body is tied to ground so this this p substrate is at 0 volt now when the gate is at low voltage there is the and p type is already on low voltage at 0 the diodes p and n plus they are see if they are the two diodes here from the substrate to each of the source and drain since the voltage at p is low and there is there is no channel here that both the diodes are off there is no current flow and the transistor is off however there is although a very weak channel between the two n plus regions that is between source and drain which can lead to a very very small leakage current now this leakage current used to be almost negligible in older technologies okay by by technology I mean the the width of this channel so this width of this channel is decreasing year by year so this is now into nanometer range so when it was when this channel length was bigger the bigger the channel length the weaker the channel here so in today's technology this is so small that the leakage current that is even when the gate is at low voltage the small current that is the leakage current is now significant part of the power dissipation we will see that later when we come to the power analysis as part of synthesis but for discussion sake we can assume that whenever gate is at low voltage no current flows and the transistor is off now when the gate when we start increasing the voltage on the on the gate the electrons in this p region they are attracted the negative charge is attracted to body so what happens is that there is an a channel of electrons which gets formed between the two n plus region because of the high voltage at the gate this channel is called an inversion layer why is it called an inversion layer because the material is p type but the the carriers the carriers here are and are electrons so it is called an inversion channel this inversion channel is actually responsible for the current flow between source and drain so now the current can flow through the n-type silicon through this channel and we say that the transistor is on now a p-mass transistor is very similar to n-mass transistor is just that the voltages that turn on and turn off the transistor are complemented so in p-type substrate was tied to 0 here the n-type substrate is tied to VDD VDD is nothing but the high voltage the gate whenever gate is low the transistor is on whenever the gate is high the transistor is off the bubble in the symbol here it indicates that it is inverted to that of as compared to n-mass if we revisit the n-mass symbol there is no bubble here however p-mass is a bubble now this let us come to VDD what does VDD mean so VDD in 1980s VDD used to be in 5 volts but as the technology has decreased the devices have shrunk in size so a higher VDD as highest 5 volts will damage the tiny transistors so that is the along with decreasing technology the VDD is also decreasing this also results into lower we into lower power so this is this this line shows the progression of VDD so right now for most of the technologies which are in production now use 1 volt some even use 0.9 0.8 volts for operation this is why you see the prevalence of battery powered devices the battery powered devices are only possible because the VDD is low if VDD was as high as 5 volts the battery would exhaust very quickly now so the let us look at transistors when they are behaving as switches so a MOS is nothing but a transistor a switch which is controlled by the gate voltage since the voltage at gate controls pass from source to drain so here we have a see that n-mass whenever the gate is 0 G is 0 the drain to source connection is broken and the transistor is off similarly when gate is 1 the drain to source connection is is the drain to source current flows and the gate is on p-moss is nothing but complementary of n-moss whenever gate is 0 the transistor is on whenever gate is 1 the transistor is off so here we see that the n-moss and p-moss both behave as switches whenever the voltage on gate is toggled from 0 to VDD let us look at a very popular the most popular in the basic device which is c-moss inverter now it is called c-moss because on the top it contains a p-moss connected to an n-moss at the bottom the source of p-moss is connected to VDD the source of n-moss is connected to ground this p-moss device is also called the pull-up device since it it is connected to VDD and it pulls a to VDD in a particular case similarly this n-moss device is called a pull-down device since it connects a to ground in one of the conditions now let us look at the probe table what happens when a is 0 or what happens when a is 1 okay when a is 1 the n-moss here let us remember that whenever gate is 1 so the gate of the gates of both n-moss and p-moss are tied together to form a whenever this gate is 1 or on a higher voltage the n-moss will turn on and p-moss will be off in this case n-moss being on it pulls a to it it pulls y to 0 so that is why it is also called a pull-down device a is 1 and y is 0 which is a typical inverter functionality similarly when a becomes 0 the n-moss switches off p-moss which is on and p-moss switching on pulls y to 1 or y to VDD so that is why p-moss is also called a pull-up device okay let us look at a slightly more complex gate which is a NAND gate so in NAND gate in case of NAND gate there are 2 and this there is a 2 input NAND gate so in CMOS technology always one input will correspond to one pair of comprising each of an n-moss and a p-moss transistor so since it is a 2 input gate for each input you have one p-moss and one n-moss so let us see how they are connected together the n-moss the pull-down circuit is a series connection of n-moss the pull-up circuit is a parallel connection of p-moss this is the logic symbol any anything can represent an NAND gate any of these two now let us look at the truth table whenever both a and b are 0 the pull-down circuit both n-moss are off and both of the p-moss are on so the output is 1 whenever any of a or b is 1 the n-moss one of the n-moss becomes on but since the other one is 0 the connection is never made however on the pull-up side whenever any of this is 0 this means 0 means that p-moss is on and since it is a parallel connection it pulls y to 1 so condition a 0 b 1 is similar to condition a 1 and b 0 that is one of the p-moss is on and one of and it pulls the y it will put pulls y to 1 to pull y to 0 both these n-moss should be on that is both a and b should be 1 so so what we see here is that when the gate type is NAND let us say the pull-down represents the complementary functionality of a NAND gate the complement of NAND gate is nothing but a NAND gate so the pull-down circuit will be nothing is the series connection of that is series means NAND gate is a series connection of the complement of the gate we want to achieve we will look at this concept in detail. Let us look at one more example of the combinational gate which is the c-moss more gate now it is just the complement of NAND gate here the n-moss are into parallel and p-moss are in series so since p-moss is in series so a and b both have to be 0 to pull y to 1 so if you look at the table here a and when a and b both are 0 then only these two p-moss will switch on and y will be connected to vdd either of a and b being 1 or when both are 1 the n-moss turns on one of the n-moss are both turned on and y is pulled down to 0 so if we notice here that the basic gates in c-moss technology are inverter NAND and NOR whenever let us say you want to make a NAND gate what you have to do is connect an inverter there will be an inverter stage after the NAND stage so that means a two input AND gate will have more will use up more transistors than a two input NAND gate that is two transistors extra for one inverter so we see that the c-moss technology is basically an inverted logic that is all the basic gates which are lowest in area and lowest in transistor form are nothing but they are either inverters that is inverter NAND and NOR these are the basic gates all other combinational gates are made out of these three gates so if you remember your basic electronics this is the reason why NAND and NOR are also called universal gates okay this is an example of a three input NAND gate it is very similar to two input the only difference being that one more input adds one more pair of transistors so since it is NAND gate so as I discussed earlier the pull down network will be the complement of that is it will be the AND connection of the n-moss that is all the n-moss will be in series the p-moss will be in parallel also if you notice that the connections are the p-moss connections and the n-moss connections are always complementary that is if the n-moss is in series the p-moss will be in parallel and the other way around okay let us look briefly at how the circuits are laid out so whenever the VSI design is manufactured it is manufactured using a set of masks what a mask means a mask is like a photograph like a photograph is developed from a negative you can say that mask is a negative from which the positive that is the photograph or the VSI circuit is made out now the minimum dimensions of mask they determine the transistor side size and in turn they determine the speed the cost and the power of the circuit there is one a very important term called feature size F which is the distance between source and train it is also the it is determined by the minimum width of polysilicon it is also called the channel it is also called channel length usually it is seen that feature size improves 30 percent every 3 years or so so the layout is usually is normalized using feature size and the all the design rules that is how let us say how wide the polysilicon would be what should be the minimum distance between the two n plus regions everything is determined on the basis of the feature size F here we define one more term which is called lambda which is feature size by 2 for example for a for a for a 0.6 micrometer process the lambda would be 0.3 micrometer we will see how lambda is used in layouts later now for example we see that there are these are simplified design rules these are the example of design rules for example this is let us say you have a metal deposition a metal one and metal two are they are made up of same material only that the orientation might be different and the width might be different that is if let us say metal two metal one is being routed in horizontal directions it might happen that the metal two is routed in vertical direction so the material is same the only thing that can differ is the width so let us say one of the design rule can be that these spacing between two metals should be at least four lambda the width should be at least four lambda so these are nothing but examples of the design rules which are normalized on the basis of feature size or lambda let us let us look at there anything you pause for a minute okay now let us look at the inverter cross section that is when the inverter is laid out and manufactured how does it look like on on layout so as we remember as we go back and see that the inverter is made up of PMOS and NMOS so this is this part is the NMOS transistor and this part is the PMOS transistor typically the substrate that is the silicon wafer is doped and with P type material with a group 3 impurity to make a P substrate since NMOS transistor needs a P substrate the N wells that is the sorry the the N plus dope the regions can be directly diffused here to make the two the source and train of the NMOS transistor now PMOS on the other hand would need a N type substrate so on the same P type substrate doping is done to make a region called N well N well is now the N well here acts as a substrate for the PMOS transistor again for PMOS for source and drain we need P plus region so they are formed here using the process of diffusion so this as an inverter the the source of the NMOS transistor is tied to ground if you remember so here we see this is a metal contact this metal so anytime we want to make a contact of the source and drain to anything we need to take we need to connect it to a metal layer so here we see the the if you see the legend this is the blue is metal one so here we see that metal one is connected to the to ground this is nothing but the source of NMOS transistor similarly the source of PMOS transistor is connected to VDD again using the metal layer now we go back and remember that the input to inverter is given using the gates that is the gate of NMOS and PMOS is tied together to form the input input A so here we see that this this region here in the middle is nothing but polysilicon that is so this this cross section is a vertical cross section so this this is a imagine a three dimensional figure a three dimensional layout so the gate here and the gate here is is actually connected here somewhere behind they both are connected to form the input A the silicon dioxide here acts as an insulator now the output again both the the drains drain of NMOS and drain of PMOS is connected together to form the output so the input is always the gate and the output is always from the drain the gate of the gates of both transistors connected together and correspondingly the drains of both transistor connected together to form the output so this is a cross section of the of the inverter now this we will we will see the these when we see the stick we will not see much of design rules in this course the design rules are very specific to technology and very specific to the kind of layout so that the picture here this this picture represents the the the the inverter layout so this is the cross section and this so this is the side view and this is the top view of the of the layout so let us look at this so the bottom part is the NMOS and the top part is PMOS the how can we differentiate we see that the region here is is N well so a PMOS you needs an N well to function so this is this part is PMOS the rail here this rail is the metal rail the rail here up on the top and on the bottom so the bottom one would be this rail would be tied to ground this would be tied to VDD the contacts here the contacts here are source and drain contacts so this this part is the both the drains are connected together and so this on the if you see on the NMOS side this is the source which is tied to ground these are the diffusion regions again this drain is connected to the PMOS drain again diffusion regions sorry this is the diffusion region again the source of PMOS is connected to VDD here this is the way the gates are connected together this is the poly silicon material so the poly of PMOS and the poly of NMOS they both are connected together so the gates are connected so this is the input part sorry this is the input part and this is this is where we apply the input voltage this is where we get the output so the transistor dimensions are specified as width divided by length that is this is the notation we use so minimum size is 4 lambda by 2 lambda if we remember go back and say see the the lambda was the feature size by 2 so feature size is the minimum width minimum channel width a technology can have since lambda is equal to f by 2 f is nothing but 2 lambda so the minimum width that can that technology can have is 2 lambda that is why the statement here says that the minimum size can be 4 lambda by 2 lambda sometimes it is called 1 unit for example in f in 0.6 micrometer process it would be 1.2 micrometer by height and 0.6 micrometer long usually to start if we keep the width as twice of the length so if we see again this is the inverter layout and the proper polarities are marked VDD, GND, AMY if you notice here that so the NMOS here has the minimum size which is 4 by 2 and PMOS is 8 by 2 that is the PMOS width is twice of the NMOS width we will see why this is needed okay let me discuss this in short for now the PMOS usually for the same width and length the PMOS is slower than NMOS due to the fact that the host mobility is less than the electron mobility so usually the factor is less than 2 but we just sound off and say that the PMOS is half is slower than NMOS by a factor of 2. So to compensate for the factor and to make the inverter balance that is to make sure that both the NMOS and PMOS are of similar strength the PMOS is usually made twice the PMOS width is twice that of the NMOS width so that is why everywhere you will see that the PMOS is designated as 2 and NMOS is designated as 1 or always the factor is 2 is to 1 okay this is so this was what we saw in this chapter was the very basic nature of the MOS circuit how the MOS is made up of gate oxide and silicon the functionality we are most interested in is the whenever the MOS acts as a switch since all the basic logic gates can be made out of a combination of switches we saw the inverter layout and this gave us an idea into how the circuit is laid out obviously at a very basic level now from next chapter onwards we look at how we will also look at look a little bit into the the transfer characteristics of PMOS and NMOS because this will again give us insight into how the propagation delays are calculated we will also see how various kinds of complex gates are made out of PMOS and NMOS plus we will see also the logic families different kind of logic families that make up the gates this ends chapter 1 thanks a lot when you can pause the record