 Namaste. Welcome to the session principles of combinational logic circuit. At the end of this session students will be able to explain the concepts of combinational logic circuit and design a combinational logic circuit. These are contents. Digital circuits are classified as combinational logic circuits and sequential logic circuits. In today's session we are going to discuss about combinational logic circuits. So what is the combinational logic circuit? So combinational logic circuit has n number of inputs let us consider a0 to an minus 1 and m number of outputs let us consider y0 to ym minus 1. So in case of combinational logic circuit outputs at any instant of time depends on the input present at that instant only. So it means that output does not depend upon the previous or past values of input or output. So there is no need to remember the past values. So it has no memory element. Now there will be no effect of sequence in which inputs are applied on the output in case of combinational logic circuit. There are various examples of combinational logic circuits which are used in digital circuits such as in arithmetic and logical system. The combinational logic circuits used are adder circuit, substractor circuit, comparators etc. In data transmission systems combinational logic circuit used are multiplexers, demultiplexers, encoders, decoders and in case of code converter systems code converters may be binary to other code conversion, bc to other code conversion or it may be gray to other code conversion. Similarly bc to seven segment converter such as there are various digital circuits where combinational logic circuits are used. Now let us see design of combinational logic circuit. Logic gates are the basic building block of digital circuits. So in combinational logic circuits basic gates and or not or universal gates as NAND and NOR are used to design. There are different ways of designing logic circuits. If you have true table from true table you can obtain Boolean algebra equation and from Boolean algebra equation you can construct a circuit or if you have only Boolean algebra from Boolean algebra you can directly design a digital circuits that is combinational logic circuit. Now let us see design of adder circuit. First of all we are going to see half adder. So half adder is also a combinational logic circuit which adds two single bit binary numbers. Now before designing half adder first of all one should know binary arithmetic. Binary addition rules are 0 plus 0 sum is 0 there will be no carry, 0 plus 1 sum is 1 with no carry, 1 plus 0 sum is 1 with no carry but when it is 1 plus 1 sum is 0 with carry 1. So according to these rules we can draw block diagram for half adder where we are considering two single bit inputs A and B. So it will give us output as sum and carry. When the next step we are going to write true table. So true table is nothing but all the combinations of input and respective output. So in case of half adder we have two inputs A and B. So there will be four combinations 0 0 0 1 1 0 and 1 1. For 0 0 sum is 0 and carry 0. For 0 1 sum is 1 and carry 0. For 1 0 sum is 1 and carry 0 and when A and B both are 1 1 we get sum as 0 and carry as 1. So from the true table we can observe that we are getting sum for the combinations when A and B are 0 1 and 1 0 and we are getting carry for only one combination when A and B are both 1. So in the next step we are writing logical equations for half adder. So logic equations are written for all the output as we here we have two outputs sum and carry we are going to write equation for sum and carry. So the equation for sum as we know that we are getting sum for two combinations 0 1 and 1 0. So equation becomes A bar B plus A B bar. The same equation is written in terms of mean terms as summation small m in the bracket 1 comma 2. And for carry we are getting output for only one combinations when A and B are 1 1. So equation of carry is C is equal to AB. So in case of mean term equation becomes summation small m in the bracket 3. So in the next step we are drawing logic circuit for the half adder. So based on these two equations first equation is sum S is equal to A bar B plus A B bar which is nothing but XOR operation. So same equation is written as A XOR B and carry C is equal to AB. So here we require two gates XOR and A AND gate. So this is the logic diagram for half adder. So let us see design for full adder. So full adder is also a combinational logic circuit which adds two single bit binary numbers along with carry if any. So difference between full adder and half adder is that. So in case of half adder if there are two bits along with that if there is a carry present then it will not consider carry but in case of full adder not only it adds two single bits A and B and it also adds carry if present. So here the answer will be 1 plus 1 is 1 plus 1 gives us sum 0 and carry 1. So let us draw a block diagram. So as we know that we have carry here. So inputs are A B and C in and outputs are sum and carry out. So based on block diagram let us write truth table. So as we have three inputs A B and C in so there will be total eight combinations of input and we are getting sum for combinations when A B C in are 0 0 1, when 0 1 0, when 1 0 0 and when A B C in are 1 1 1 and we are getting carry out that is C out here for combinations when A B C in are 0 1 1, 1 0 1, 1 1 0 and 1 1 1. So from this truth table we can observe that we are getting some for four combinations of input and carry out that is C out for four input combinations. So logic equation for full adder the same equation is written as summation small m in the bracket 1, 2, 4, 7. For carry out the equation and same equation is written as summation small m in the bracket 3, 5, 6, 7. So there is a technique where we can reduce logical equations. So take a pause here and recall which technique is used for reducing or minimizing the logical equation. So the technique which is used to reduce or minimize the logic equation is K map. So K map is a graphical representation where the min terms or max terms from a equation are represented on the map and putting once into the cells 1, 2, 4, 7 what we get is so there will be no pair, quad or octet. So we have to consider individual terms. So equation of sum becomes as earlier. So there will be no reduction in this equation. Now let us write K map for carry out. So by putting once into the cells 3, 5, 6, 7 we get three pairs and these three pairs will reduce carry out equation as C out is equal to AB plus AC in plus BC in. Now let us design logic circuit from these two equations sum and carry. So for sum as we know that there are four terms here we require four AND gates and output of four AND gates are given to OR gate which you will give us sum as output and for carry out equation is AB plus AC in plus BC in. So we require three AND gates here and output of three AND gates again given to OR gate that will give us C out. These are references. Thank you.