 Hello and welcome to this presentation of the STM32 System Window Watchdog. It will cover the main features of this peripheral used to detect software faults. The Window Watchdog is used to detect the occurrence of software faults. The Window Watchdog can be programmed to detect abnormally late or early application behavior. It is best suited for applications required to react within an accurate timing window. Once enabled, it can only be disabled by a device reset. An early wake-up interrupt can be generated before a reset happens to perform a system recovery or manage certain actions before a system restart. The Window Watchdog offers several features. The user can program the timeout value and the window width according to application needs. It can generate a reset under two conditions. When the down counter value becomes less or equal to 0x3f or when the Watchdog is refreshed outside the time window. It can generate an early wake-up interrupt when the down counter reaches 0x40. The early wake-up interrupt can be used to reload the down counter in order to avoid a reset generation or to manage system recovery and context backup operations. As shown in the figure, the Window Watchdog uses the APB clock or PCLK as reference clock for its time base. The PCLK is provided by the RCC block. This clock is divided by 4096 and by a value programmed by the application. The application can also program the reload value of the down counter bits T6 to 0. The window width is controlled by bits W, 6 to 0. The STM32MP1 includes a Window Watchdog dedicated to Cortex M4 usage. WWDG1 is connected to the APB1 bus and the APB clock must be enabled via WWDGEN bit prior to use of the WWDG1. The WWDG1 early interrupt output is connected to the NVIC and to the GIC so that both Cortex M4 and A7 can handle the interrupt. The WWDG1 reset output is connected to the RCC and generates a reset of the Cortex M4 only. In addition, this reset output is connected to the EXTI in order to activate the Cortex A7 when a window watchdog reset occurs. This feature allows the Cortex A7 to restart properly the Cortex M4 if needed. It is possible to select if the watchdog will be frozen when the Cortex M4 is in debug mode, core halted. Please refer to the MPU debug unit, dvgmcu description for details. Note as well that window watchdog is frozen when the Cortex M4 is in C stop or standby mode but can remain active when it is in C sleep mode. This diagram illustrates how the window watchdog operates. When the 7-bit down counter rolls over from 0x40 to 0x3F the watchdog asserts the reset. This happens if the application software does not refresh the window watchdog on time. The early wake-up interrupt or EWI, if enabled, can be generated when the down counter reaches 0x40. If the software refreshes the watchdog while the down counter is greater than the value stored in bits, W6 to 0, a reset is generated. This happens when the application refreshes the watchdog too early. No interrupt is generated in this case. To prevent a window watchdog reset, the watchdog refresh must happen while the down counter value is lower than the time window value and greater than 0x3F. This is illustrated by the green area. The refresh operation consists of reloading the down counter with bits T6 to 0. To enable the window watchdog clock, the corresponding window watchdog-enabled it in the RCC block must be set to 1. Note that once the APP clock for the watchdog is enabled, the application cannot disable it. Only a system reset can disable the watchdog clock. A low-power-enabled it can be set as well and the application wishes to keep the window watchdog activated even if the CPU is in sleep mode. The down counter uses the APB clock PCLK divided by 4096 and again divided by a division ratio selected by the application. It can be 1, 2, 4, 8, 16, 32, 64 or 128 as defined in the WWDG CFR register. The formula shown in this slide lets you determine the watchdog timeout value. When a system reset occurs, it is possible to identify which parts cause the reset thanks to status flags provided by the RCC block. The window watchdogs can be one of the sources. The early wake-up interrupt or EWI can be used in order to perform emergency tasks before the reset occurs, such as data logging, data protection, watchdog refresh in order to prevent the reset or other emergency tasks. The EWI interrupt occurs whenever the down counter value reaches 0x40. It is enabled by setting the EWI bit in the WWDG CFR register. The EWI interrupt is cleared by writing 0 to the EWIF bit in the WWDG SR register. The window watchdog is active when the Cortex-M4 is in C-run and C-sleep modes. It is not available in stop or standby modes. In C-sleep mode, the window watchdog clock can be disabled by clearing the corresponding low power enable bit located in the RCC block.