 Hello, and welcome to this presentation of the STM32 independent watchdog. It covers the main features of this peripheral, which can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The independent watchdog is used to detect and resolve malfunctions due to software failures. It triggers a reset sequence when it is not refreshed within the expected time window. Since its clock is an independent 32 kHz low-speed internal RC oscillator, or LSI, it remains active even if the main clock fails. Once enabled, it forces the activation of the low-speed internal oscillator, and it can only be disabled by a reset. One of the main benefits for applications is its ability to run independently from the main clock. The independent watchdog offers a wide range of timeout values. From 125 microseconds to 32 seconds, it is clocked by a 32 kHz RC oscillator, which cannot be disabled when the independent watchdog is enabled. It generates a reset when the program timeout value elapses, or when a watchdog refresh occurs outside a program time window. This window feature is optional and not present in all independent watchdogs. It is possible to enable automatically the independent watchdog after a system reset. It is possible to define the behavior of the independent watchdog in debug, stop, or standby mode. The independent watchdog registers are located in the core voltage domain, while its functions are in the VDD voltage domain. Two clocks are needed. The APB clock is required in order to access registers. The LSI clock is required for the functional part of the watchdog. This architecture allows the independent watchdog to work even in stop and standby modes. A programmable 8-bit pre-scaler is used to divide the LSI oscillator frequency. The 12-bit down counter defines the timeout value. The STM32H7 microcontroller includes two independent watchdogs, or IWDGs. IWDG1 is dedicated to CPU1 usage, and IWDG2 is dedicated to CPU2 usage. For each independent watchdog, it is possible to select the hardware or software start via option bytes. For each independent watchdog, it is possible to select if the watchdog will freeze when the associated CPU is in debug or core halted mode. Please refer to the microcontroller debug unit or dbgmcu description for details. The control of the behavior in stop or standby mode is common for both independent watchdogs. When OTP freeze stop is activated, the independent watchdogs are frozen when the system is in stop or standby mode. When OTP freeze standby is activated, the independent watchdogs are frozen when the system is in standby mode. Both watchdogs are connected to the APB4 bus of the D3 domain. Both watchdogs can perform a system reset handled by the RCC block. This diagram illustrates how the independent watchdog operates. When the down counter reaches zero, the watchdog reset is activated. This happens when the application software did not refresh the window watchdog on time. If the software refreshes the watchdog while the down counter is greater than the values stored in the window register, then a reset is generated as well. To prevent a watchdog reset, the refresh must occur when the down counter value is other than zero and lower than the time window value. The independent watchdog hardware is enabled by the device's option bytes. If the hardware mode is enabled after every system reset, the watchdog automatically loads the down count with 0xFFF and starts to count down. To prevent any reset, the key register must be refreshed at regular intervals before the counter reaches zero and within the window if this option has been selected. The IWDG software start is configured in a few steps. The first step is to write the key register with value 0x0000CCCC, which starts the watchdog. Then remove IWDG register protection by writing 0x000055555 to unlock the key. Set the IWDG prescaler in the IWDGPR register by selecting the prescaler divider feeding the counter clock. Write the reload register IWDGRLR to define the value to be loaded in the watchdog counter. After accessing the previous registers, it is necessary to wait for the IWDG SR bits to be reset in order to confirm that the registers have been updated. Two options are now available. Enable or disable the IWDG window option. To enable the window option, write the window value in the IWDGWINR register. Otherwise, refresh the counter by writing 0x0000AAAA in the key register to disable the window option. The IWDG timebase is prescaled from the LSI clock at 32 kHz. The IWDGPR prescaler register can divide the LSI clock frequency by 4 up to 256. The watchdog counter reload value is a 12-bit value written in the IWDGRLR register. A formula can be used to determine the independent watchdog timeout. The independent watchdog time is based on the LSI period and its prescaler, as well as the selected watchdog counter reload value. Note that the reset and clock controller, or RCC, of the product provides registers giving the source of the reset. In that way, the application can check if a reset is caused by an independent watchdog. The IWDG can be active in all modes.