 So, welcome to this lecture on VHDL in the course digital system design with PLDs and FPGAs. In the last lecture we were looking at some examples of given a circuit how to write the code and given a VHDL code how to infer what is the circuit which could be synthesized from that code and so on. And we could not complete that so I am planning to complete it and get to the digital system design for few lectures before maybe we come back to the VHDL little bit again go to some other topics okay. So let us have a look at what we have done last class, last lecture. So last lecture we have looked at the ripple order. So in the ripple order it is simple you know you have a full order cascaded and the problem is a delay and we said for carry look at add basically it is like you know writing the truth table and implementing it or working out from the full order it means that you have this two equation one is for sum, one is for carry. The trouble with the ripple order is that the say Ci plus 1 is you know kind of derived from ai, bi and ci, ci is you know coming out of the previous stage so it ripples you know it adds to the delay. So what the carry look at adder does is that you take this and substitute here from the starting with the c0 like c1 is a0, b0 or a0 or b0 and c0 and when it comes to c2 it is a1, b1 and so on. So c1 whatever is a c1 equation is substituted, expanded at a two level kind of structure only difference is that this is made common you know ai, bi and ai or bi because that is used everywhere so that is made common. So there is a another kind of level of gates that is all what it happens so you get as a substitution goes it gets expanded you know one product term becomes extra because of this process and you have you can see that this is g0, p0 add to a level of gates. So you have three levels of gates for the carry and then the xr followed with the xr so you have around kind of five gates delay for all the stages you know that is what is achieved by the carry look at adder and we have implemented the sum and gi, pi in a loop and the carry equations are explicitly written not a big deal because even if it is to write a 32 bit it is not a big problem you can write it and ultimately at least in the case of plus most of the time we use the plus operator depends how it is implemented and mostly it will be ripple adder in FPGA it will result in a built in adder resource which we will look at it later when we come to the FPGA part and we have looked at as an example the shift register and most of you would have learned somehow you would have coupled this shift with the register but you should know that there is a register then there is a shift operation and when you want to shift by kind of say one bit then it is a matter of wiring say d6 go to d7 d0 go to d1 this is d1 d dash 1 and you append a 0. So it is just a wiring and destination could be a different register in most practical applications it will be a different register you know only very less cases where the destination is same as the source because you have a data path where the data kind of you know goes through a pipeline. So there is no way you can push it back you know many a time so it goes all the way unless the algorithm itself has an iteration back then you iterate over the data path the example will be some kind of encryption schemes where you do it iterate it over which can be unfolded but then that is a very costly kind of operation so it is iterated over back through the data path and but when you need some kind of variable shift say you want a shift register with shift left shift right or you shift by 1 bit shift by 2 bit then you need to have a configurable shift that is achieved by a MUX. So here I am showing a shift left in that case the Q6 will get the Q5 for shift left and if it is shift right then Q6 will get Q5 and if it is a parallel load it will be coming you know coming from the external inboot and so on. And there is a select line depending on the number of paths and this is replicated so you have an 8 bit register then you have 8 MUXs and so I said you can view it as 8 separate MUX or a huge MUX it depends how you view it and the coding also can be different depending on that. So the variable shift is done through a multiplexer and we have seen a universal shift register where you have shift left shift right and a parallel load and that is a code and we have seen we have written a case within the clock event clock is equal to 1. This one shows separate MUX as a loop and the second code shows a kind of single MUXing essentially it is same but like I am talking in terms of the hardware now but in terms of the syntax in the VHDL this is kind of loop and this is kind of what to say a vector assignment otherwise the circuit wise there is no difference there could be difference because it all depends how the synthesis tool kind of infer the structure and how it is mapped to the underlying hardware and all that there could be difference for us to try it out. Every when we play with the tool we can take some example and have a look at how the synthesis tool handle the various type of coding and so on. So we have seen another example given a block diagram how to code as I said we can code a register with the preceding logic using a single process and here it looks like there is some logic preceding it and some logic following it but this being a kind of you know cyclic this can come over here that is what we have done and then you can write a process like clock and reset is there if reset is 1 then z is 0 otherwise upon the clock if lock is 1 then it is Q plus AL it is B. So that is what is shown here reset is 1 Q is other 0 upon the clock if LOC is 1 then Q gets Q plus AL Q gets B. It is very simple to write the code and this is another example we have got the VHDL code and we kind of work back to find what is a circuit which is implemented by this and from this we could like you have an a is equal to 1 then output is 0 otherwise upon the B so a is a reset B is a clock. So this is a comparison y is compared the output is compared with some input and if it is 1 then the data is shifted you know the output is shifted version of the present output the next output is a shifted version of the present and that is it otherwise it will hold the value so you get a as reset B as a clock then the y is compared with C if it is 1 then a shifted version of the y along with the D goes in here otherwise it is kind of re-circulated that is hardware you get and this is where we have kind of stopped ok. This is another code a VHDL code our aim is to kind of find at least draw the block diagram of the circuit and infer what is the function of the circuit ok. So at the entity level it is very simple you have 2 inputs which are 4 bit U and V and a single output which is 8 bit ok and there is no clock or reset so you are sure at least I have not shown the code but this being a practical code there is no mention of something kind of sounding like clock and reset so this is a combinational circuit which takes 2 4 bit values and gives an 8 bit value. Now coming to the architecture before the begin we have some declaration a D type 1 it is a new data type which is an array of 4 locations each location is 4 bit and we are declaring a y of this type ok. Now that means there is a y3 y2 y1 y0 each of which is 4 bit ok. Now another data type which is again 4 location 8 bit and we have declared x as that type that means you have x3 x2 x1 x0 and we have each of x3 x2 x1 x0 is 8 bit and we have defined a constant that is for easy kind of coding maybe for kind of some symmetry we will see in the code which is temp which is a 4 bit factor which is all 0's ok so 4 0's ok. So we will see the code so remember this U and V are the inputs 4 bit W is output 8 bit we have some intermediate signal y which is 4 location 4 y's y3 y2 y1 y0 each of 4 bit x3 x2 x1 x0 each of 8 bit ok. Now let us go to the code so look at this you know there is a generate loop now as I said U and V are the input and y is 4 kind of values 4 indexes y3 y2 y1 y0. So the loop is going from 0 to 3 now look at it y of 0 is U and V of 0 replicated 4 times. So this is kind of aggregating it. So we know that U is a 4 bit vector which is an input so you have U3 U2 U1 U0 which is ANDed with U3 is ANDed with V0 U2 is ANDed with V0 and so on. So all of the 4 bit is kind of masked with V0 ok for y0 when it comes to y1 the same U is kind of masked with repetition of V1s y2 is nothing but U and kind of sorry y3 is U and V3 all V3s and so on ok. So you get 4 y0 y1 y2 y3 which is nothing but U is masked by this bit ok. So I am going to show this pictorially you have a 4 bit U vector U3 U2 U1 U0 the first operation is that you take there is a V which is going from V3 V2 V1 V0. So initially the U is masked with all V0 say V0 V0 V0 V0 that is what is done here and you get y0 which goes from 3 2 1 0 then next is V1 then it is masking and you get y1 3 2 1 0 V2 then you get y2 and you say V3 then you get y3. So it is going like this the arrow is going like this 1 by 1 and here the arrow is going like that you know. So maybe I should have made it kind of opposite but then I hope it is clear V0 make y0 V1 y1 V2 y2 V3 y3 ok. Now maybe you get an idea what could be what possibly could be the circuit but let us wait you know let us look at go ahead see the next part of the code. So this is a very simple code but this is how the circuit is coming up. So I think keep this in mind let us go to the next part of the code ok. Now we are now here we form the y's from U and V that is the game and in the second part we are going to make x from y and term and you know that the term is just 0 ok. So let us look at it the x0 which is not in the loop probably which could have been in the loop but let us see x of 0 is term 3 down to 0 which is nothing but 4 0's and y of 0, y of 0 is this 4 bit. So you have 4 0's then appended with y of 0 ok. Now we get to the loop, loop start with because 0 is already made loop is going from 1 to 3 and you say let us take the first index x of 1 because x of 0 is already there x of 1 which is 10 3 down to y that means 3 down to 1. Here it was 3 down to 0 4 0's but here it is 3 0's then y1 now. So the earlier was y0 was appended now we appended the y1 it is appended with 3 0's y1 and temp i-1 that is 1-1 temp 0 down to 0 that means 0 only 1 bit. So you put a 0 here that means 3 0's y1 and 1 0 ok. Now you can guess when it comes to x2 this will become 3 down to 2 then you have 2 0's y2 and it is 2-1 1 down to 0 2 0's and the next loop when it is x3 it is 1 kind of you know 3 down to 3 1 0 y and 3 0's and in addition you see as the loop goes initially we have 4 0 and y now when it comes to x1 it is 3 0 y and 1 0 plus this is the previous one. So this 2 are added when it comes to x2 whatever those 2 added is added with the new value and so on and when you get x3, x3 is assigned as w which is output ok. Now let us look at that picture. So we initially put ok now come back to this we had u we had v each of the first least significant bit of v0 is mass you get y0 another bit is mass then you get y1 next bit is mass with u y2 y3 now you are forming all 0's then put the y0 then you shifted version of y1 is added together then you shifted version of y2 is added to it and shifted version of y3 is added to it and you get w. So it is you are getting the point so you know that it is nothing but shift and add. So it is like it is multiplying and if you look at this this is nothing but forming the partial product. So you have a multiplicand which is 4 bit u3 u2 u1 u0 you have a multiplier which is 4 bit. So the first partial product is formed by the least significant bit of the multiplier and added with this multiplicand you get the first partial product. Then the v1 is added with this you get the second partial product v2 is added with this then you get the third partial product and then v3 is added and you get the fourth partial product ok that is what is done here. So you get four partial products and now when it comes to this structure it is nothing but partial products are shifted left you know one by one and it is added together. So it is like you know the partial products are added to get the product ok. So this though I am showing this adder there is this can be kind of it is showing three adders and parallely it is added because it is a generate loop it is not that the same adder is used each time a new adder is used because it is replicated. So you get a parallel adder. So it is a multiplier but it is not a kind of iterative multiplier it is a parallel multiplier and the name of this multiplier is called array multiplier because you form an array of the partial product and you add it parallely. So it is an array multiplier it is a 4 bit unsigned array multiplier. Only thing is that normally when you refer to the textbook to avoid the rippling something called instead of a ripple adder a carry save adders are used here you know that when you add this there is a rippling here then there is a rippling here. It is possible to avoid the rippling kind of because the idea is that say you are adding these two bit it does not matter whether the carry comes here or carry comes here. So it is possible to put the carry of this stage along with this here similarly carry of this stage can come here the carry of this stage can come here. So that gives a kind of to reduce the ripple otherwise it ripples ripples ripples and you know so you will get kind of 4 plus 4 8 rippling it is possible to avoid the rippling using carry save adders. But this is a kind of the idea is not to kind of design the array multiplier with the carry save adder it is a practice in kind of working out from the code written you know inferring the circuit which is implemented. And as I have shown though the code looks little crazy it is very easily you know you can write and work out the underlying hardware ok. So only thing is that it has to be done systematically you have to work on the pen and the paper ok. When I say pen and the paper definitely you can write on your tablet or the note tool or I do not know when this course is being recorded in November 2013 maybe somebody is watching in 2016 or 17 if at all it is done then I do not know what is the technology maybe whatever may be the technology you can kind of you work it out ok. Literally work it out on whatever tool you have I would say on a paper pencil then things will be very clear there is no kind of ambiguity you know I have taught you what the code means and now it is a matter of patiently working systematically then you will get what is the circuit. And in the process you can add like suppose somebody has given a code like that you can definitely infer that the ripple adder is being used there is lot of rippling maybe we can replace this ripple adder with the carry save adder and make things faster the critical path delay can be reduced and so on. So that is a advantage of kind of working the hardware from the VHDL code so that should be kept in mind. So let us move ahead one more example that has to be let us look at this example so I want you I want to design a synchronous 4 bit up down counter with the parallel load feature ok that means it is a synchronous counter 4 bit it should count up when the direction is 1 down when the direction is 0. And there is a load signal and 4 bit input when the load is 1 it should load the counter with the input value and depending on the direction when the load goes low depending on the direction it should go up or down ok. And we will first we will do is that we will write the block schematic then we will write the behavioural code you know step systematically from this block schematic which is kind of drawn. So you know that the 4 bit counter needs a 4 flip-flops you have the clock and reset ok. So like when the reset comes the count is 0 and when the clock comes the game starts the first thing is that you know that in a parallel load counter we need to have the priority for the load. So we will put a MUX here ok to the D and the select line is load and when that is 1 we supply the input ok if it is 0 then we have to put the count part ok. So let us put that when so we put a 2 to 1 MUX at the input because that is the highest priority and we have seen that the highest priority will come near to the D ok near to the D because that is the one which gets effect first. So when the load is 1 this D in gets loaded into the D if it is 0 now the direction comes. Now we have 2 things to do if there is a direction is 1 then it up counts direction is 0 it down counts. So what we do is that we put a 2 to 1 MUX here the select line is a direction if direction is 1 then what we do we have to increment this because it is Q. So you take this Q back put a plus 1 to the 1 input of MUX. Similarly if direction is 0 then Q has to be decremented so Q is put through a minus 1 and put to the MUX ok. So let us put that so we have a 2 to 1 MUX there is a direction signal if it is 1 Q is taken back to as input then we have a plus 1 which goes to the MUX and if it is 0 Q is going through a minus 1 it goes to the 0 and it goes there ok. So now that is simple we have 4 flip flops reset clock which is common we have the highest priority load which goes to the first 2 to 1 MUX and load is 1 this goes there load is 0 depending on the direction now direction is 1 then Q is Q plus 1 else Q is Q minus 1 ok. And that simple now actually like the design is over now if you look at this you know that this entity has say reset as input single bit clock as input single bit load as input single bit direction is input single bit DNS and input which is standard logic vector 3 down to 0 which is 4 bit then we have a count which is output which is 3 down to 0 4 bit that then we this structure shows that count is also input to it and we know that the VHDL does not allow. So we declare an internal signal called Q and then we use Q as in the to write the code and in the architecture statement region we assign this Q to the count ok. Now if you look at VHDL code symbol process clock and reset if reset is 1 Q gets other 0 else if clock given clock is equal to 1 under that if load is 1 Q gets dn else if direction is 1 Q gets Q plus 1 else Q gets Q minus 1 end if sorry yes end if that is it. So that is the old code the moment you see this the code is there is no need to write the code you know it is a mechanical process. So it is possible to generate the code if you want you know somebody draw a block schematic it is possible to generate the VHDL code out of the block schematic ok it is for a computer science student is very easy you know from this kind of structure to generate a VHDL code it is very straightforward like you have a tool to draw like the moment you put the draw like you are only allowing the designer to draw. So you know what is happening and you keep you know adding the template you have a template code then you can keep you know generating the VHDL code it is very easy. So let us look at the kind of the code you have the library and we have standard logic 1164 then standard logic unsigned because we are going to use a plus as I said clock reset load direction is 1 bit dn is 4 bit input count is 4 bit output then the Q is the same as count which is a signal 4 bit count gets Q then we start the begin ok in the begin count gets Q then you write process clock reset begin if reset is 1 Q gets other 0 else if clock given clock is equal to 1 then underneath all that is coming behind and this has highest priority next this has a priority. So if load is 1 then Q gets dn else if direction is 1 then Q gets Q plus 1 else Q gets Q minus 1 end if ok. So and this end if and this is the memory end if this is the combinational circuit if this represents the combinational circuit with kind of priority and this represents the memory end if because it is no else and end process end architecture. So that is very simple and that is how you should write the code very straightforward there is nothing to worry but if somebody say like you give this spec and you start like that straight away without any clue whatsoever about the circuit and most people try to do that you know they kind of some vague idea and you know start assigning things and things can go wrong because you will be wondering you know something goes wrong then you will be playing with the if you say ok let us instead of putting the if else here you put something else write another nested if and so on because you have no clue on what is the circuit and you will waste lot of energy in going but if you know as we have learned you know what is the meaning of this syntax as far as the circuit is there concerned then it is very easy very very very easy to write after practice these kind of structure will be in your mind you do not need to kind of expand it you can just show as a block with the load direction and some way to indicate which is which has kind of priority over the other and things like that some kind of notation you can use then straight away you can code it it is very easy. So I think it is a some kind of logical place to stop for a while because we have taken quite a lot of VHDL but that is to put you in a strong footing. So that when we go to the tool take a case study try to implement your kind of tarot. So in this class we have looked at the carry look at adder the VHDL code then we have seen basically the ripple adder carry look at adder adder then some you know examples of some random circuit how to code it then basically we have looked at the code of an array multiplier and worked out the underlying circuit and without even bothering about what is the functionality of course you are writing in kind of exam and you have such a kind of question then you are kind of finding like you know you have a shortage of time then definitely you can guess and jump to conclusion but when you are doing the serious design in a design team you should not do that you should do as I kind of as I have shown but when you are with a serious design you should not guess anything you should work it out and in for what is going on and the last thing we have looked at is that given the spec of a counter how to draw the block diagram and how to write the VHDL code as a one to one you know what is shown in the block diagram is a code written give it to any synthesis tool it is going to generate the same circuit you know maybe it is mapped to some inbuilt block as a single unit or multiple unit it does not matter but then we are not sure maybe the multiplexer in there is implemented using some special resources within an FPGA but that apart from that you know apart from the technology the block schematic which is generated by the synthesis tool will be exactly same as what you wanted you know what you have drawn on the paper or what you have written the code you are 100% sure about that. So that is a kind of thing I want you to do as a designer and do not think that anything complex will have you know much more difficult than this because ultimately we have seen that you know you have a complex circuit then we are going to break it down hierarchically as data path in controller then we are going to data path itself is going to be broken down to this level of detail and then you can write the code in a very very very straightforward way you do not have to kind of you do not have to be very happy that you get a C code to VHDL compiler you can do that if you are in short of time or a software engineer is trying to do the hardware design and so on. But I do not see any big point in doing that definitely the tools will improve as we go along the standard but still it will be kind of template base it cannot be kind of artificial intelligence and things like the machine learning and things like that but maybe it will come like that but at least for the time being it is kind of you know there is underlying templates you map the you infer the structure architecture and try to map it to the standard structures and so on. So let us stop this the VHDL part here and let us for at least two lectures let us get back to the digital design so that we can continue maybe with the VHDL little more we will go hand in hand. So let us move on so let us come back to the digital system design part now very quickly I want you to run through the last thing we have done hopefully I am able to kind of I am putting the thing correctly. So the last thing we have discussed in digital design was a case study if you have not familiar kind of if you have forgotten or if you have not taken that part of the looked at that part of the lecture go back and look at it ok. So what we have done was to we have an ADC what we have tried normally ADC is kind of interface to a host CPU or a microcontroller or a processor what we are trying to do is that to kind of take the load of the processor by having a controller controlling the ADC and putting the data to a temporary storage and when is kind of full the host will read it that was the idea. And we found that the best candidate for this is FIFO because you know you write the data in order you read the data in order there is no and it is a one way data flow. So you put the FIFO so you get you put a controller give the start of conversion end of conversion comes to the controller in addition controller has the clock and reset it gives the FIFO right. And when this becomes full kind it interrupts the host and host will read it and host give a start for you know controlling the whole operation when it is start is one it keeps on doing it and when it is 0 it stops and this is the data path FIFO and we are at least in this case we have assumed FIFO is there already and we have looked at the controller. And first thing we have made some assumptions you know that it is and we have drawn a timing diagram wait for the start when the start comes give a source wait for an end of conversion give a write signal then we said that this is a can be a narrow pulse in one state you can give an output but this should be of some width and we need to generate that time properly. So we decided to put a counter as a subsystem which is controlled the reset of which is controlled by the same controller or state machine. And when it is equal to it is decoded for a particular value then gives a time. So the idea is that when the FIFO write is given the reset is removed and it starts counting and you wait for this time when it reaches that pulse get that pulse then you put back the reset and the terminate the FIFO. So we have updated the timing diagram added this when you put this low the reset is removed wait for this. And from this we have worked out an algorithm like you know wait for the start give start of conversion wait of end of conversion give FIFO write remove the reset wait for the signal and terminate everything go back to the same thing ok. And that was the control algorithm and we have written a state diagram and the exactly similar thing. And so there are inputs, transitions, states and the output and we have decided to use the FIFO for state binary encoding. So 00, 01, 10, 11 and from this state the input transition you can work out the next state table, state output you can work out the output table. So we have done that you have this is the controller. We have basically the state variables or the flip flops which gives the present state in our case to flip flop and that along with the input decode the next state and upon the clock next state is loaded. And in each state the present state output is decoded from the present state as a function of the present state or as a function of input and the present state. If it is only the function of present state is more where is a function of present state and input then it is a melee. And we have written as I said from the input and the present state and the transition this table then you get an equation for D1 and D0 in terms of the present state and the input then you can know minimize implemented similarly for the output you write the output in terms of the present state and you get output as a function of present state you form the equation and minimize it and that is the whole methodology and basically up to the state diagram is what the designer has to put effort then the tools come into picture in all minimization and ultimately to test and debug you use some kind of equipments and the designers involvement is there. Here designer gives some kind of inputs and that is what we have done you know we have seen the whole process of designing of course the data path has to be designed. So let us now take some issues in the state machine itself the controller. The first thing is that we know that we have happily put like when we discuss the state diagram you see here okay the state diagram is here. So we have shown upon the reset that means at the beginning when the power on reset come it should start with S0 okay it can be 0 0 it can be any state it need not be 0 0 but it can be any state but the game is that this reset has to be implemented you should not forget that you know that is very dangerous you work out everything but you forget to implement reset in state machine then you power on it can come anywhere okay it is very dangerous luckily we have only 4 states and 2 flip flops but assume that we have say 6 states then we need to use 3 flip flops and there are 8 states there will be some unused state and by you power it on without a reset and if it goes to some unused state we do not even know what is the behaviour of the state machine very dangerous. So it has to be properly reset so that is what we are going to see that. So let us look at that okay this is the state machine we have the flip flops present state next state logic and output logic. So very simple if you have reset asynchronous reset in the flip flop just use the connect the power on reset to that and at the power on it will become it will come to the starting state. Once it comes to the starting state then you have the control you know you are the one who is designing the state machine and you can at the end of the iteration you can bring it back to the whatever state you require you need not come back to the starting state depending on the application it can go to some other state and wait for some input but you have to at the beginning at the power on you have to bring it to a starting state and that is where it is used and this is like in VHDL coding this is simple because this is combined with the flip flop okay. So you can read this as a kind of process for a flip flop then this reset is implemented along with that flip flop you know as the asynchronous reset of the flip flop. Suppose take the case where the flip flops in the technology whatever the technology you use be it ASIC or an FPGA assume that this reset is not available then you and there is suppose there is no reset at all in the flip flop then what we have to do is that we have to introduce a synchronous reset as the name suggests it is something to do with the D. So it is very simple you add an input reset here okay and change the next state logic and we have seen the truth table can be changed or we are going to write the VHDL code. So in this summer we are going to say if reset is 1 then this next state is the starting state then that is done okay. So if this is not available then use a synchronous reset but not both you know so I have removed that and if use a synchronous reset if it is not available use a synchronous reset. So that is done and from the experience what we have with the kind of data path design a clever student can already infer what could be the circuit in terms of you know we have shown for a counter with the load signal this reset as the priority like say there is input there is present state but definitely we know that synchronous reset as the priority. So if you look at it is equal and do kind of putting a MUX here okay and the reset is the select line and when the reset is 1 a 0 goes there otherwise this next state logic comes here. Like if you write a code for synchronous reset and give it to the synthesis tool that is going to happen at the output of previously written code previously generated circuit you are going to have a 2 to 1 marks where the select line is reset and you get a 0 okay that is what is happening. So I am kind of reinforcing what we have learned probably I could have shown the picture but you know it takes a lot of effort to draw these pictures and put it. I have already invested lot of energy so but I think you can kind of imagine what is basic idea here so that is about the power on reset and when it comes to the VHDL we will go back to the VHDL coding of the state machine though it is nothing kind of I mean nothing great because we know how to code flip flops or registers we know how to code the combinational circuit because this is a combinational circuit this is a combinational circuit you could we have seen that you could combine the output logic with the next state logic. But after all it is combinational circuit and we know how to code the combinational circuit so but yet we will see that because the controller is one important part and we will see how to properly code it and it is also there are different ways of coding it but it is very specific to maybe the tool there may be 6 different ways of coding it but your tool may not understand everything then there is a problem. So we will see that we will go back to the coding of the VHDL let us look at the next topic okay. Now in this very conveniently we have shown a clock okay and that is what all the text book do kind of they show a clock okay and say the clock is there but what should be this clock okay. So what should be the frequency of the clock that is the question okay. Many a times it is not address and you are kind of most of the time when you are in an academic you are answering some kind of most of the time some exam where it is enough that a line is drawn and you write the clock okay. So you are saved by that but in real life you have to give a clock okay and so we have to decide what should be the clock okay. So definitely you must be getting some kind of idea saying that this probably can suffer or tolerate a range of frequencies okay. Let us assume let us try to find out what could be the maximum clock we can apply to this okay and what could be the minimum clock okay. So let us look at the maximum clock and let us look at the minimum clock okay. So the maximum clock you must be already getting the idea it has something to do with the delay of this logic delay of the flip flop and delay of this logic and we have already seen the maximum frequency of the state machine which is nothing but the maximum frequency of a data path or a register to register path. This is a sequential circuit but you have a data path as a pipeline it is all same you know you have some registers some flip flop its output is going through a combinational logic and is going to some other flip flop. In this case if you have Q1 and Q0 Q1 output may go through some circuit go to D1 or D0 and so on okay. So that could be 4 paths you know Q1 Q0 D1 D0 2 by 2 you have 4 paths. So you know that if you consider that the clock comes there is a TCQ delay there is a delay through the combinational circuit and that data has to be here setup time before. So the clock period should be greater than TCQ max, TCOM max plus T setup max okay. And we have also with the incomplete information we have this given a clock the output is kind of appear here after TCQ and T output logic. So whichever is greater whichever this is greater or this is greater we choose definitely if it goes through some other combinational circuit to a register we have to consider all that. And that is what when you really design the tool is going to look at the whole path you know this is just a picture but ultimately when you design this is going through a register output logic some combinational logic and ultimately it is going to a register and the tool is going to analyse that you know that you should keep in mind. So let us put the maximum frequency okay. So we have a maximum clock frequency which depends on delay of the clock maximum clock frequency or the minimum clock period is T clock min should be greater than max of TCQ max plus TNSL max plus T setup max or TCQ max plus TOL max and there could be kind of some more terms here. But kind of with the information we have we are putting I am putting this you know you can add that but suppose you have designed a state machine and you find the maximum frequency say 1 gigahertz this kind of this can tolerate and is it a good idea to clock it at 1 gigahertz. Maybe the system which is controlling which is the data path which is controlled by say we have some data path which is which the state machine controls suppose that is working at say 100 megahertz what is the point you know that is dissipating so less power but this is furiously clocking at 1 gigahertz dissipating lot of power because it is switching. So there is no advantage in working at the maximum frequency we have to see how much minimum we can go because in terms of the power dissipation that is the best thing to do like without like after all the state machine alone cannot do anything as long as it allows the data path to proceed at the desired throughput desired frequency then we should choose a frequency of the clock for the state machine such that the data path works properly at the desired it should give the desired performance then we can minimize power in the state machine. So let us think let us ask this question what should be the minimum frequency okay that is the great that is the right question to ask so maybe I think you should think what is the what should the minimum frequency depend on okay so that is the question to ask the answer is maybe I will put something we are you know basically controlling a data path so these inputs are coming from the data path some output and this outputs are going to the data path input and what we are trying to do is that we are trying to look at various input step through various sequences and control that data path okay so essentially it has got something to do with this input and something to do with the output because that is where the game is okay there is nothing extra because there is a clock there is a reset everything else is coming from the data path so it must got something to do with the input something to do with probably something to do with the output okay. So let us ask this question okay so what should be the minimum clock frequency okay now to illustrate I will kind of put some inputs and let us see that okay so assume that we have 3 input to our state machine okay that means we are looking at this say these inputs are 3 inputs from the data path it is some output of data path in 1 into in 3 okay to make our life easy we are assuming they are all kind of you know square waves okay which is not true in real life you do not get anything like this you may not even find a scenario where very rare scenario where everything is kind of square wave but let us put this okay so that is where so I am trying to put a clock you know the best thing is that when you try to analyse something then you should put some simplest case simple assumption suppose in maths you are trying to do something say a kind of matrix multiplication with which is a 10 by 10 and you are trying to understand something maybe you are trying to understand something about Eigen values and Eigen vectors and so on. So it is very easy suppose you put a 5 by 5 matrix and trying to work out you will not get any kind of intuitive idea but the moment maybe you take a simple case of 2 by 2 matrix and a kind of 2 by 1 vector and you try to infer these you know draw a kind of graph draw a picture then you will get some intuitive idea. So every time when you try to kind of understand some fundamental you put simple thing you know do not make very complicated. So that is why I put a very simple picture which is not real life then once you get the basic idea then we can bring it to the next level of reality we can bring back to the reality close to real life. So what I am showing is that I have shown 3 inputs and you know that this in 3 is a some frequency maybe 100 megahertz into is 50 megahertz and in 1 is 25 megahertz okay. So now I put a clock okay to see like we have to see what is the minimum kind of frequency. So I just put a clock okay of course I have worked it out I have manipulated it for you to understand but look at this okay and this is working on the positive clock edge okay like that and you see that when this clock comes say in 1 is 0 the next clock 1 in 1 has changed no problem it is detected within a clock period again it is still 1 no problem it has gone to 0 that is detected you take the into when the clock came into was high it is detected then it went low then this is detected and this change is detected but you take look at this in 3 and you see that the clock edge comes and that is sampled and this is 1 and there is a transition to 0 it comes back to 1 but when the next clock comes it is still 1 it is still 1 it is still 1 that means there are some changes in one of the input but since we have chosen a particular clock frequency this is not detected at all. So this shows that this clock frequency is not going to work maybe this is too low a clock period okay but suppose I put a clock like this say now there is a positive clock edge yes it is detecting that it is 0 and when the next positive edge it is detecting that it is 1 next positive edge it is detecting that 0. So it shows that the clock frequency of the state machine has got something to do with the input changes okay. So definitely we know that there is a change here so if a clock has to come the clock period has to come within this thing. So we can say as I to start with I make a statement saying that the clock frequency should be twice that of the maximum clock frequency okay. So we are coming to probably the end of the lecture today's lecture I will continue I will complete this portion. So we looked at two part one is the reset use async reset or async reset and the maximum clock frequency depend on the delay of the blocks minimum clock frequency has got something to do with the rate of change of the input to the state machine which is output of the data park. So please go through whatever we have covered in this lecture revise it learn well and I wish you all the best and thank you.