 Hello and welcome to this presentation of the STM32WL5 power controller. Power management functions and all power modes will also be covered in this presentation. STM32WL5 devices feature flex power control, which increases flexibility in power mode management and further reduces the overall application consumption. Run mode can support a clock system running at up to 48 MHz with only 70 microamps per MHz. STM32WL5 devices support 8 main low power modes. Low power run, sleep, low power sleep, stop zero, stop one, stop two, standby with RAM retention, standby and shutdown modes. Such mode can be configured in many ways, providing several additional sub modes. Note that for RF operation, the system cannot go below standby with RAM retention mode, as a minimum set of contexts needs to be maintained. In addition, STM32WL5 devices support a battery backup domain called VBAT. The high flexibility in power management provides performance with Cortex-M4 consumption of 70 microamps per MHz and simultaneous Cortex-M0 plus consumption of 28 microamps per MHz also running CoreMark together with outstanding power efficiency demonstrated by the ULP MarkCore profile score equal to 359 at 1.8 volts and 223 at 3 volts. The STM32WL5 has several key features related to power management. Several low power modes down to 30 nanoamps while it is still possible to wake up the MCU with an event or an I.O. For only 255 nanoamps, 32 kilobytes of SRAM can be retained. Many peripherals can wake up from the various low power modes. Dynamic consumption is down to 70 microamps per MHz executing from flash memory. A battery backup domain called VBAT including the RTC and certain backup registers. Several power supplies are independent, allowing reduction of MCU power consumption while some peripherals are supplied at higher voltages. Thanks to the large number of power modes STM32WL5 devices offer high flexibility to minimize the power consumption and adjust it depending on active peripherals, required performance and needed wake-up sources. STM32WL5 devices have several independent power supplies which can be set at different voltages or tied together. The main power supply is VDD, supplying all I.Os, the reset block, temperature sensor and all internal clock sources. In addition, it supplies the standby circuitry which includes the wake-up logic and independent watchdog as well as the radio. VDD is monitored by the BORS circuitry. VDD SMPS supplies the switch mode power supply step-down converter. Its output, the FBS MPS, supplies the CPU with most of the digital peripherals and the SRAMs. The flash memory is supplied by both the FBS MBS and VDD. STM32WL5 features several independent supplies for peripherals. VDDA for the analog peripherals, VDDRF for the sub-gigahertz radio. The internal reference voltage used by the analog block can be output on the VRF Plus pin to supply external circuitry for the application. A backup battery can be connected to the VBAT pin to supply the backup domain. The SMPS supplies the digital core and radio LDOs. The SMPS operating mode, on and off, will follow the device modes. The SMPS supports switching on the fly when requested by firmware. To remove any noise from the SMPS during ADC conversions, software may switch on the fly the SMPS mode. The STM32WL5 supply configuration used to be selected by hardware. For the best power performance, use the SMPS configuration. For the lowest cost, the LDO configuration can be used. The main power supply VDD ensures full featured operation in all power modes from 1.71 up to 3.6 volts, allowing supply by an external 1.8 volt plus or minus 5% regulator. Device functionality is guaranteed down to 1.61 volts, the minimum voltage after which a brownout reset is generated. Sub gigahertz radio operation is allowed down to 1.95 volts. Other independent supplies are provided to allow peripherals to operate at a different voltage. The VDDS MPS is connected to the same supply as VDD. The analog power supply VDDA can be connected to any voltage other than VDD. When the analog to digital converters or comparators are used, the VDDA voltage must be greater than 1.62 volts. When the digital to analog converter is used, VDDA must be greater than 1.8 volts. When the voltage reference buffer is used, VDDA must be greater than 2.4 volts. A backup domain is supplied by VBAT, which must be greater than 1.55 volts. The backup domain contains the RTC, the 32.768 kHz LSE external oscillator, and the backup registers. The power supply supervisor allows dynamic power supply management. STM32WL5 devices embed power management on main VDD, analog VDDA, VBAT supply input, switch mode power supply, VFBS MPS, and sub gigahertz radio, VDDRF. The main VDD supervision allows reset management and voltage detection via the power voltage detector, or PVD, when VDD crosses the selected threshold. The PVD can be enabled in all modes except standby modes. Seven thresholds can be selected by software. The brownout level can be used to provide switching on the fly of the SMPS when VDD drops below the threshold level. On the analog VDDA supply, a supervision circuit selected via PVM detects when VDDA crosses the threshold. The PVM can be enabled in all modes except standby modes. On the VBAT supply, a supervision circuit selected via PVM detects when VBAT crosses the threshold. On the SMPS VFBS MPS supply, a supervision circuit will reset the core when the supply is too low, less than 1.4 volts. On the sub gigahertz radio VDDRF supply, a sub gigahertz radio end-of-live detector is available. The sub gigahertz radio supply detector can be enabled to be operational when the sub gigahertz radio is active. The power supply supervisor guarantees a safe and ultra-low-power reset management. STM32WL5 devices embed an ultra-low-power brownout reset, or BOR, which is always enabled in all power modes except shutdown mode. The BOR ensures reset generation as soon as the VDD drops below the selected threshold, regardless of the VDD slope. Five thresholds from 1.7 to 2.95 volts are selected by OptionBite, programmed in flash memory. A power voltage detector can generate an interrupt when VDD crosses the selected threshold. The PVD can be enabled in all modes except standby and shutdown modes. Seven thresholds can be selected by software. In addition, an external pin can be used to compare voltages. The BOR consumption with the 1.7-volt threshold is included in the datasheet. The STM32WL5 MCU embeds one peripheral voltage monitor to detect if the VDDA supply is present or not. This comparator has wake-up from stop-mode capability. The PVM3 compares the VDDA voltage with the 1.65-volt threshold intended for the comparator's analog-to-digital and digital-to-analog converters. The PVM1, PVM2, and PVM4 are not present in STM32WL5. To guarantee any of the supply sequences on the application, power isolation has been implemented and is active by default. It is the role of software to enable the needed supplies by removing the power isolation. The ADC and DAC voltage references can be provided either by an external supply voltage or by the internal reference buffer. This allows improvement of the converter's performance by providing an isolated and independent reference voltage. The Vref plus pin and thus the internal voltage reference is not available on all packages. In these packages, the Vref plus is double-bonded with VDDA and the internal voltage buffer must be kept disabled. The voltage reference is provided through the VDDA pin in these packages. The application software can decide to disable the SMPS when performing ADC or DAC conversion to reduce noise. In that case, the application can decide to disable the radio subsystem during this conversion. The battery charging feature allows charging of a supercap connected to a VBAT pin through an internal resistor when VDD supply is present. The charging is enabled by software and is done either through a 5 kilo ohm or 1.5 kilo ohm resistor depending on software. Battery charging is automatically disabled in VBAT mode. The STM32WL5 system contains three subsystems. The CPU1 Cortex-M4, the CPU2 Cortex-M0 Plus, and the sub gigahertz radio subsystem. Each of the three subsystems can operate independently being in one of its operating modes, C-run, C-sleep, or C-stop. Peripherals will only be clocked when the associated subsystem is in C-run mode or C-sleep when enabled in sleep mode. The system resources such as RCC, PWR, EXTI, and SRAM2 connected on the shared bus will always be clocked when one of the CPUs is in C-run and the system is in run mode. The other peripherals on the shared bus may be enabled to operate with CPU1 and or CPU2. The CPU1 bus matrix peripherals may be enabled to operate with CPU1 and or CPU2. The sub gigahertz radio system is connected to the bus matrix via the sub gigahertz serial peripheral interface. The sub gigahertz radio system may operate when both CPUs are in C-stop mode. In this case, all other peripherals and all bus matrixes are stopped and the system may be in stop or standby mode. Each CPU can decide independently which low power mode to use. Stop 0, stop 1, stop 2, standby, or shutdown. Each CPU can decide which wake-up source, RTC, sub gigahertz radio, GPIO, or peripheral will wake it up. When both CPUs enter WFI and or WFE, the hardware mechanism executes the compatible request. It selects the highest low power mode compatible with the requirements from both CPUs. One CPU can wake up without the need to wake up the other one if not required. When the STM32WL5 wakes up from stop mode, according to the wake-up source, only the CPU registered for this wake-up source is restarted. The other one stays in WFI or WFE with its clock stopped. When the STM32WL5 wakes up from standby modes, in accordance with the source, only the CPU registered for this wake-up source is restarted. The other one stays under reset mode. Run mode, run range 1, run range 2, and low power run and frequency selection changes are centralized to avoid conflicting configurations. This includes selections of the system clocks as well as low power enable and voltage range and flash memory configurations. The sub gigahertz radio subsystem operates autonomously and will enter and exit low power modes on its own. It does not impact the CPUs and system low power modes. The sub gigahertz radio low power timer and a CPU may wake up the sub gigahertz radio subsystem from its peripheral low power mode. According to the requirements of the CPU1 and CPU2, the power controller hardware mechanism manages how the STM32WL5 reaches a given state. When CPU1 allows standby mode and CPU2 allows only stop-to mode, the system enters stop-to mode. Note that only the CPUs can place the system in LP run or LP sleep modes. The sub gigahertz radio may be active down to system standby mode, independent from any CPU and system low power mode. The sub gigahertz radio shall be disabled prior to the CPUs entering the system in shutdown mode. Power management allows control of the device power supply based on system operating mode. The system operating mode depends on the individual CPUs and radio operating modes. The system is in run mode whenever one of the two CPU subsystems is in C run or C sleep mode. The system enters stop or standby modes when both CPU subsystems are in C stop mode. In system run mode, the device power supply can be scaled according to the required performance. Up to 48 MHz in range 1, 16 MHz in range 2, and only up to 2 MHz in low power run mode. A CPU enters the C stop mode when executing a wait for interrupt or WFI or wait for event or WFE with a deep sleep bit set. The system state also depends on the operating modes of the other CPU and the radio system. The CPU on bus matrix clock is only stopped when the other CPU has no allocated peripherals on the CPU on clock domain or the other CPU is also in C stop mode. The system may only enter stop or standby mode when both the other CPU and the radio system are in C stop mode. The system only enters standby mode when allowed by both CPUs. When a CPU wakes up from its C stop mode, it has to know from which mode the system has woken up. For this, the CPU has a few dedicated flag bits, SBF, stop F, and stop 2F. These bits inform the CPU about the state of the system and which parts of the clock and peripherals may need to be re-initialized. These CX-SBF or standby and CX-STOP-NF or stop flags have to be tested by the CPU software when waking up from C stop modes and after CPU reset. They enable the CPU application to selectively reprogram its context, RAM, peripherals, and clocks. This figure gives the complete overview of the power modes in relation to the CPU's operating modes. Whenever a CPU is in C run or C sleep mode, the system is in run mode. Low power stop, standby, and shutdown modes are only entered when both CPUs are in C stop mode. The low power mode is selected by the low power mode select or L-P-M-S bits. Each CPU has its own low power mode select bits and the system enters the highest-consuming low power mode selected. From stop and standby modes, each subsystem can be awakened independently by its own enabled wake-up sources. From shutdown mode and reset, only the CPU-1 Cortex-M4 is awakened. It is up to the Cortex-M4 application software to wake up the CPU-1 Cortex-M0+. The sub gigahertz radio peripheral operation has no impact on the CPU's and system operating mode. Each peripheral clock can be configured to be on or off in run and low power run modes. By default, all peripheral clocks are off except the flash interface clock. The SRAM-1 and SRAM-2 clocks are always on in run mode. When running from SRAM-1 or SRAM-2 in low power run modes, the flash memory can be put in power down mode thanks to software and the flash clock can be switched off. The flash memory must not be accessed when it is switched off. Consequently, interrupts must be mapped in SRAM using the Cortex-M4 vector table offset register. Here is a summary of the PWR control-related interrupts. The run mode, thanks to voltage scaling and the low power run modes, offer flexibility between required performance and consumption. In run mode range 1, the system clock is limited to 48 MHz and the internal and external oscillators and the PLL can be used. In run mode range 2, the system clock is limited to 16 MHz and the internal and external oscillators as well as the PLL can be used, but must be limited to 16 MHz. In low power run mode, the system clock must be limited to 2 MHz and the PLL cannot be used. Sleep and low power sleep modes allow all peripherals to be used and feature the fastest wake-up time. In these modes, the CPU is stopped and each peripheral clock can be configured by software to be gated on or off during the sleep and low power sleep modes. These modes are entered by executing the assembler instruction wait for interrupt or wait for event. When executed in low power run mode, the device enters low power sleep mode. Depending on the sleep-on-exit bit configuration in the Cortex-M4 system control register, the MCU enters sleep mode as soon as the instruction is executed or as soon as it exits the lowest priority interrupt subroutine. This last configuration allows you to save time and consumption by saving the need to pop and push the stack. Batch acquisition mode is an optimized mode for transferring data. Only the needed communication peripheral plus 1DMA plus SRAM 1 or SRAM 2 are configured with clock enable in sleep mode. Flash memory is put in power down mode and the flash memory clock is gated off during sleep mode. Then it can enter either sleep or low power sleep mode. Note that the I2C clock can be at 16 MHz even in low power sleep mode allowing support for 1 MHz fast mode plus. The use art and LPU art clocks can also be based on the high-speed internal oscillator. Typical applications are sensor hubs. STM32WL5 devices feature two stop modes with full retention. Stop 0 and stop 1, which are the lowest power modes with full retention and fast wake-up time to run mode at maximum 48 MHz. The contents of SRAMs and all peripheral registers are preserved in stop 0 and stop 1 modes. All high-speed clocks are stopped except the ones used as kernel clock for peripherals capable of operating in stop modes. The 32.768 kHz external oscillator and 32 kHz internal oscillator can be enabled. Several peripherals can be active and wake up from stop mode. System clock on wake-up can be the internal high-speed and multi-speed oscillators up to 48 MHz with only a one microsecond wake-up time from SRAM or five microseconds from flash memory. Stop 1 consumption is lower than stop 0 but supports less active wake-up peripherals. STM32WL5 devices feature one stop mode with partial retention. Stop 2 mode with partial retention provides still fast wake-up time to run mode at maximum 48 MHz. The contents of SRAMs and the CPUs and some peripherals are preserved in stop 2 mode. All high-speed clocks are stopped except the ones used as kernel clock for peripherals capable of operating in stop modes. The 32.768 kHz external oscillator and 32 kHz internal oscillator can be enabled. Several peripherals can be active and wake up from stop mode. System clock on a wake-up can be the internal high-speed and multi-speed oscillators up to 48 MHz with only a one microsecond wake-up time from SRAM or five microseconds from flash memory. Stop 1 consumption is lower than stop 0 but supports less active wake-up peripherals. When comparing stop modes, stop 0 mode has the highest consumption as it keeps the main regulator on. Stop 1 mode consumption is higher than stop 2 mode consumption but the wake-up time is shorter and the number of active peripherals is higher. Stop 2 mode only provides partial retention including all memories, both CPUs and some peripherals. The following peripherals are not retained and need initialization after wake-up from stop 2 mode. HSEM, LP TIM 2 and 3, I2C 1 and 2, USART 1 and 2, SPI 1, SPI 2S 2 and sub gigahertz SPI, TIM 1, 2, 16 and 18, DMA 1 and 2 and DMA MUX, ADC, DAC, AES, PKA and True RNG. The I2C address recognition is functional in all stop modes and can generate a wake-up event in case of an address match. Only one I2C is supported in stop 2 versus 3 I2Cs in stop 0 and stop 1 modes. The UART byte reception is functional in all stop modes and can generate a wake-up event in case of start detection or byte reception or address match event. Only the low-power UART is supported in stop 2 mode. In other stop modes, all UARTs and the low-power UART can generate a wake-up event. When clocked by the internal or external low-speed oscillator or when clocked by an external pin, the low-power timer can wake up the MCU with all its events. In stop 0 and stop 1 modes, all low-power timers are supported, whereas only LP TIM 1 is supported in stop 2 mode. To allow the CPU 1 to re-initialize the clock system when exiting from stop modes, the stop hold function holds the CPU 2 until the CPU 1 has re-initialized the system. To ensure this, a wake-up from stop mode interrupt holds the CPU 2 and wakes up the CPU 1 with a wake-up hold interrupt. Once the CPU 1 has re-initialized the system, it releases the CPU 2 hold. The standby mode is the lowest power mode in which 32 kilobytes of SRAM 2 can be retained. The automatic switch from VDD to VBAT is supported and the IO levels can be configured by independent pull-up and pull-down circuitry. By default, the voltage regulators are in power-down mode and the SRAMs and the peripheral registers are lost. The backup registers are always retained. The ultra-low-power brownout reset is always on to ensure a safe reset regardless of the VDD slope. Each IO can be configured with or without a pull-up or pull-down, which is applied and released thanks to the APC control bits. This allows control of the input state of the external components even during standby mode. Wake-up sources are the sub-GHz radio, PVD, RTC, TAMP, IWDG and three configurable wake-up pins. The wake-up clock is MSI with a frequency of 4 MHz. The wake-up sources are the three wake-up pins and the RTC. The shutdown mode is the lowest power mode of the STM32WL5 with only 30 nanoamps at 1.8 volts. This mode is similar to standby mode but without any power monitoring. The brownout reset is disabled and the switch to VBAT is not supported in shutdown mode. The LSI is not available and consequently the independent watchdog is also not available. A brownout reset is generated when the device exits shutdown mode. All registers are reset except those in the backup domain and a reset signal is generated on the pad. The 80-byte backup registers are retained in shutdown mode. The wake-up sources are the three wake-up pins and the RTC. When exiting shutdown mode, the wake-up clock is MSI at 4 MHz. The backup domain allows you to keep the RTC functional and to preserve the backup registers in case the VDD supply is down thanks to a backup battery connected to the VBAT pin. The backup domain contains the RTC clocked by the low-speed external oscillator at 32.768 kHz. Three tamper pins are functional in VBAT mode and will erase the 128-byte backup registers also included in the VBAT domain in case of intrusion detection. The backup domain also contains the RTC clocked control logic. In case VDD drops below a certain threshold, the backup domain power supply automatically switches to VBAT. When VDD is back to normal, the backup domain power supply automatically switches back to VDD. The VBAT voltage is internally connected to an ADC input channel in order to monitor the backup battery level. When VDD is present, the battery connected to VBAT can be charged from the VDD supply. Here you can see the summary of all the STM32WL5 operating modes. Three bits are available in the flash option bytes to prohibit a given low power mode. When cleared, an option bit configures reset generation when entering shutdown mode. Another bit configures reset generation when entering standby mode. And the last bit configures reset generation when entering stop one or stop two modes. One bit is used to configure the behavior of the BORHX threshold, either as a reset, as in the STM32L4 family, or to automatically switch the SMPS into bypass mode. Note that switching back to SMPS mode when VDD increases depends on the application. Three bits are also available in the debug control register for debugging in sleep, stop and standby mode. When the related bit is set, the power is kept on all logic in standby and stop two mode, and the HCLK and FCLK clocks remain on to keep the debugger active. This maintains the connection with the debugger during the low power modes and continues debugging after wake up. Remember to clear these bits when the MCU is not under debug, because the consumption is higher in all low power modes when these bits are set, due to the fact they force the clocks and the regulators to remain enabled. In addition to this training, you can refer to the reset and clock control and interrupts trainings, as well as those for all the peripherals with wake up from stop capability.