 Hello, and welcome to this presentation of the STM32G4 System Memories Protection. It will cover the different means for protecting code and data. Memory protections have been designed for different purposes. Protected memories are the flash memory, the core-coupled memory, or CCM, SRAM, and the backup registers. A read protection, for example, will prevent the dumping of embedded software code through an external access and will protect the developer's intellectual property. A write protection will prevent certain flash sectors from being accidentally erased by a load overflow in a software or data update procedure. STM32G4 microcontrollers provide several features for protecting code and data located in flash memory and backup registers. In addition to these typical memory protections, the STM32G4 also introduces a new mechanism to ensure the safe execution of sensitive firmware. The following slides will describe all these protection features. The following means are provided for code protection purposes. RDP, Readout Protection, PC Rop, Proprietary Code Readout Protection, WRP, Write Protection. Secure user memory protection is a new feature of STM32G4 microcontrollers. It ensures the safe execution of sensitive applications in addition to code and data protection. Readout Protection, or RDP, is a global mechanism that prevents external read access to flash memory, option bytes, CCM, SRAM, and backup registers. An external access can be gained by using a JTAG connector, a serial wire port, or the boot software embedded in SRAM. Three levels of RDP protection are defined from Level 0, which offers no protection at all, and Level 0, Level 2, which has full and permanent protection. Protection levels will be described in the following slides. PC Rop is a memory access protection against code dumping. It is used to protect the intellectual property of the code. The protected firmware remains executable, but read and write access performed by the CPU executing malicious third-party code, such as Trojan horse, are prohibited. The write protection mechanism prevents accidental or malicious write and erase operations. Secure user memory is a flash memory area with a specific protection mechanism to ensure the safe execution of sensitive firmware in addition to code and data protection. All protection mechanisms are configurable via the STM32G4 option bytes. Note that once the secure boot has been executed, the secure user memory is no longer accessible until the next reset. This slide highlights the differences regarding the flash memory implementation between STM32G4 3X and 4X, called Category 2 microcontrollers, and STM32G4 7X and 8X, called Category 3 microcontrollers. Number of banks is 1 for Category 2, 1 or 2 for Category 3, depending on the D bank option bit. The page size which provides the minimum erase granularity is 2 kilobyte for Category 2, 4 kilobyte for Category 3 with single bank, and 2 kilobyte for Category 3 with dual bank. Regarding protection features, the Category 2 microcontrollers have one write protected area, one PC Rop, and one secureable memory area, while Category 3 microcontrollers have 2 write protected areas, 2 PC Rops, and 2 secureable memory areas. When the lowest RDP level, level 0, is set, the device has no protection. All read or write operations, if no write protection is set on the flash memory, the CCM SRAM and the backup registers are possible in all boot configurations, such as flash user boot, debug, or boot from RAM. Option bytes are also changeable in this level. Level 0 is the factory default level. In level 1, read protection is set for the flash memory, CCM, SRAM, and the backup registers. In this level, protected memories are only accessible when booting from user flash memory. Whenever a debugger access is detected or boot is not set to a user flash memory area, any access to the protected memories generates a system hard fault, which blocks all code execution, until the next power-on reset. Note that option bytes can still be modified in this level, making it possible to remove the protection. This mechanism is explained in the next slide. We have seen in the previous slide that it is possible to modify option bytes in level 1. It is then possible to remove the protection by changing the protection level to level 0. This protection level regression will cause the flash memory, the CCM SRAM, and the backup registers to be mass erased. Flash areas protected by PCROP or configured as secure user memory can be erased or left unchanged depending on their erase policy configuration. Readout protection level 2 provides the same protection as in level 1, but the protection becomes permanent. Option bytes cannot be modified, so once the RDP protection is set to this level, there is no way to modify it and level regression with mass erase mechanism is no longer possible. This level must only be considered in the final product when the development stage is completed. Note that to ensure that there are no back doors, this protection cannot be bypassed even at ST factory. This slide shows the possible transitions between each readout protection level. It is always possible to raise the protection level, but regression is only possible between level 1 and level 0. When the RDP is reprogrammed to the value 0xAA to move from level 1 to level 0, a mass erase of the flash main memory is performed. Backup registers and CCM SRAM are also erased. The OTP area is not affected by mass erase and remains unchanged. If the bit PCROP-RDP is cleared in the flash PCROP-1ER register, the full mass erase is replaced by a partial mass erase that is successive page erases in the blank where PCROP is active, except for the pages protected by PCROP. This is done in order to keep the PCROP code. Note that the RDP level is coded in one option byte. Level 0 is coded by a 0xAA value. Level 2 is coded by a 0xCC value and level 1 is coded by any value other than 0xAA or 0xCC. This table summarizes the different types of access authorized for the flash memory and backup registers according to the readout protection or RDP level, configured boot mode and with debug access as seen in previous slides. PCROP means proprietary code readout protection. Third parties may develop and sell specific software IPs for STM32 microcontrollers and original equipment manufacturers may use them when developing their own application code. In order to protect the software intellectual property or IP, the code must not be copied or read. The PCROP's purpose is to protect the confidentiality of third-party software intellectual property code against malicious users independent of the RDP level setting. The protected firmware can only be executed by the Cortex-M4 core. Any other access like DMA, debug and data read, write and erase is strictly prohibited. To be compliant with this constraint, the firmware must be compiled with the appropriate compilation option. For example, minus execute only for keel tools. Without this option, constants are interleaved with functions in the read-only section called the literal pool. The Cortex-M4 MPU does not support execute only access permissions. The proprietary code readout protected areas in flash memory are defined through the option bytes. Each PCROP area is defined by a start page offset and an end page offset related to the physical flash bank base address from 16 bytes or 32 bytes up to the full bank, 16 bytes for Category 2 devices and Category 3 devices with dual bank, 32 bytes for Category 3 devices with single bank. The areas are protected against data accesses. Note that sectors protected with the PCROP feature are also protected against write access, offering protection against unwanted sector write or erase operations. The PCROP protection can only be removed by an RDP level regression from Level 1 to Level 0. When executed, this mechanism triggers a full mass erase of the flash memory. Depending on the PCROP RDP option bit, the PCROP areas are erased when the RDP protection is changed from Level 1 to Level 0. The write protection protects code and non-volatile data from unwanted or accidental erasure. This protection is only available on the flash memory. The write protection can be set on a selection of flash memory pages only. When a page is protected, it cannot be erased or programmed. Any attempt to write access the sector will cause a flash memory error. If at least one page is write protected, a mass erase of the flash memory cannot be performed. The protection needs to be removed first. The purpose of the Securable Memory is to store code and data available during the boot time that become inaccessible once the boot program sets a control bit. The typical use case consists in performing an authentication and possibly decryption of the software image present in the flash memory by using cryptographic keys contained in the Securable Memory. The authentication and decryption programs are also stored in the Securable Memory. Option bits are used to set the size of the Securable Memory in page units. Base address is always 0x8 million for Securable Memory Area 1, which corresponds to Cortex M4 reset vectors. Securable Memory Area 2 starts at address 0x080400. When the SecSize field in the option bytes is equal to 0, Securable Memory is not implemented. This field can only be modified in RDP level 0. When software sets the SecProte iBit in the flash CR register, the Securable Memory number i is no longer accessible. In case of Secure Boot used to perform image authentication and decryption, the SecProte iBit is set to 1 when the authentication is successful, just before branching to the first instruction of the image. Once the SecProte iBit is set, it cannot be cleared by software. The only way to clear this bit is to apply a reset. Of course, code present in the Securable Memory may decide to erase a part or the Securable Memory. Furthermore, changing the flash read protection level from level 1 to level 0 triggers the erasure of the Securable Memory. Note that the code present in the Securable Areas can also be protected against read and write access by mapping it into Proprietary Code Readout Protection, or PC Rop Areas. Changing the RDP level from level 1 to level 0 will erase these PC Rop Areas, whatever the value of the PC Rop RDP bit. Only the contents of PC Rop Areas outside the Securable Memory address range will be preserved. Taking control of the Cortex M4 by using invasive debug can be temporarily disabled by programming appropriately the DBGSWEN control bit. For instance, the Secure Boot can decide to clear this bit before performing authentication and decryption, and then to set this bit to 1 to re-enable invasive debug once the authentication is successful. In the STM32G4, three different boot modes can be selected, boot from embedded SRAM, boot from system memory, and boot from main flash memory. Executing a Secure Boot from Securable Memory implies that the boot area is the flash memory. To disable the other boot areas, the bootlock option bit has to be set in the FlashSecR register. This option bit can be set unconditionally. However, resetting it is possible only when RDP level is 0, or RDP is changed from level 1 to level 0, which causes a full mass erase. Please refer to the flash memory training to learn more about the memory architecture, option bytes, and flash memory operations.