 Hello everyone, welcome to lecture on test bench for binary adder. Now, at the end of this session, students will be able to build the test bench for binary adders and also verify the VHDL module designed for binary adders with the help of this test bench. Right. Now, before starting with the actual session, let's pause the video and think about what is a full adder circuit. If you remember in the previous video lectures, we covered the different VHDL modules. In that we covered binary adders. So, in that we studied full adder right. So, this is the circuit for full adder circuit right. Now, if you observe over here, in full adder there are three inputs A, B and C in right and we are getting two outputs that is sum and carry right. Now, to write a test bench for any module or any device or circuit, we required previously designed VHDL code for that right. So, before starting with the test bench for a binary adder, let's have a look at the VHDL code for binary adder. So, we already designed this VHDL code in previous video lectures. So, we just have a glance on that right. So, this is the circuit for four bit binary adder right. So, you can observe over here, there are four full adders are used right. Each one is having three inputs two are A and B, A of 0, B of 0, A of 1, B of 1, A of 2, B of 2 and A of 3, B of 3 and the third input for each full adder is nothing, but this carry. So, for first full adder which is applied externally C in and for remaining three full adders whatever the output carry you are getting from previous full adder, it is connected as a input right. You can see over here right and each full adder is giving you another output that is a sum. So, S of 0, S of 1, S of 2 and S of 3 and last carry from the full adder is nothing, but your final carry of four bit binary adder right. What you can get from this is what you are applying two input signals which are of four bit and you are getting the sum which is of also four bit and a single bit carry right. Now, let us study the VHDL code for this four bit adder. We know that each every VHDL code is having a three different section. First part is a library declaration part. So, that is supposed to be done we have to include the libraries. Then second important part is a entity part. Now, in the entity we have defined that how many ports are there, what are the inputs and what are the outputs right, what is the type of those inputs. So, here we can see that from the previous slides if you look at the figure you will understood that A and B are the input which is of bit vector type having four bits in that. So, it is having a range three down to zero then sum that is S is output it is again a vector. So, that is why it is having a range of three down to zero four bit vector right and carry is there. So, C out is a carry which is a out, but a single bit. So, that is why the type of this mention is a bit right. Now we are done with the entity now third important part of your VHDL code is a architecture. Architecture is nothing, but it describe how your circuit is going to behave right. So, in this one what we are did we are used a single bit full adder as a component. So, while using any design as a component you must have a code for that VHDL complete code I am saying complete that is means it should have a library declaration it should require entity part it should require architecture part right. So, for this single bit full adder we are already stored a complete code and that one we are using as a component. So, the right to write the component syntax is what we have to write the keyword component and then the same entity name whatever you used in a previous code. So, full adder is a name then the same port declaration as we did for the single bit full adder. So, that code over here after that we required one time signal. Because if you look at the figure in the previous slide internally connected signals are there that is carry from previous full adder is connected to the in as a input to the next full adder that is seen which is internally connected. So, for that purpose we required time. So, time is declared over here right. Now, after that for each full adder we have to write the instantiation right. So, there are four full adders one bit full adder. So, for each one we have to return the component instantiation right. So, syntax for that is what you have to write the component name then port map then you have to map the signal which are associated with that component. So, for full adder F A 0 we have signal associated that A of 0 B of 0 then temp of 0 that is the C out your output signal S of 0 that is sum out right and then C in that is temp 1 right these are the associated signal. As we complete all these component instantiation we have to update the C out final C out which is nothing, but the temp of 4 bit right then we have to end the architecture. So, this is the short summary of your VHDL code for 4 bit binary adder. Now, let us if you have perform the simulation for this code you will get the output like this right. So, we can verify that you can pause the video and you can verify the different conditions if the input is this and A and B are the inputs with the 0 0 what will be the output in that case if you make the variation in the input signal what will be the output again that you can verify that you can pause the video and verify the waveform. Now, let us go for the test bench test bench is used to verify whether the design VHDL code for that particular device or circuit is functioning properly or not. So, for that purpose again the syntax is there right. So, let us go through the syntax first you have to write the first library declaration part same you did for the VHDL code design right. So, library declaration is there after that you have to write the empty entity means the entity is supposed to be there as you did in a VHDL code writing, but in that you are not writing anything the entity is supposed to be empty right. So, empty entity is there then the next part is architecture. Now, in the architecture you are going to write the component declaration as we did in a previous code here also you are writing the component declaration. So, component declaration is done for the unit under testing that is why it is called UUT unit under testing. So, component declaration is done with the name ADDR that is adder 4 4 bit adder. So, that is why I mentioned the name adder 4 right. Then you have to mention the inputs and outputs associated with that components right. So, here A, B, C, in and S are the inputs and outputs associated with that component right. Then also you have to mention type of each one A is of vector B is also of vector type then C in is a single bit sum that is S out signal is also a vector type right and C out your final carry that is a bit type right. Once you done with the component declaration you have to end the component right. Then next part comes that is signals what are the inputs and output signals associated with that. So, you have to mention the signals signal A and B are taken which is again type of bit vector. Why we require inputs and output signal over here these input and output signal you are going to map with your component and then you are going to verify the waveform. So, that is why as you mentioned the signals in the components same signals you have to taken as a inputs and outputs right. Once you done you have to start the architecture begin now here your actual architecture begin right. Now, in the architecture you have to write the component instantiation as we did in a VADL code design right. So, same over here UOT is a component instantiation name then you have to write the component name that is Iderford that we can created in a previous slide then you have to port map the inputs and outputs. So, port mapping is done A is mapped with the A, B is mapped with the B then your C in is mapped with the C in then some S is mapped with the S and C out is mapped with the C out means these signals are mapped with the signals which are declared in a component you can previous slide right. Next we have to write the processes. So, stimulus process is we have to write now this process is written for A. So, that is for the in a signal A. So, that is why the name mentioned over is stimulus process A right. In that what we did we did we have created a process in that we have make A value assigned to A is what 0 1 0 0 then we have waited for 100 nanosecond then again A is updated with the value again we waited for 100 nanosecond. Here our process ends stimulus process A ends same process we have to write for B signal B. So, same process is done B is an updated with the value 1 1 1 1 4 bit signal right then we waited for 100 nanosecond then B is again updated with this value 0 0 1 1 again waited for 100 nanoseconds and then a process of B signal ends. Similarly, we did for the C in that is carry in we applied signal with the 0 value single bit signal it is that is why it is only having 0 then we waited for 100 nanosecond right then we have end the process right and once you done with the all the stimulus processes you have to end the architecture. So, that is why end architecture right this is the simulation output if you perform that code and if you check the simulation you can see over here A and B are the inputs of 4 bits O here and values are here you can check that we have written stimulus process for 3 signals A B and C in and we have updated the value only 2 times 1 A is having value 0 1 0 0 0 then again we are updated that value with all 1 and again B is updated with 0 0 1 1 right. So, we have changed the value of both the signals only 2 times. So, the you can see the change over here this is the value of A in one iteration after 100 nanosecond the value change to this then for B the value is this after 100 nanosecond we have changed this and for that what is the output we can see over here see out carry and sum right. So, if these waveforms are working as per your VHDL design model then you can say that our code is working properly and if you are having any error in that suppose your code is not functioning as per your test bench your test bench gives you the output in a compilation window or you can say console window that the error in a simulation and it shows where that error is occurred right. So, this is how can you can verify your VHDL design model with the help of state test bench right. So, these are the references. Thank you.