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Chirp generator in the phase accumulator on FPGA

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Published on Jul 14, 2014

Developer: Sergey G. Badlo
H-page: http://raxp.radioliga.com
Download: http://raxp.radioliga.com/cnt/s.php?p...

BACKGROUND

1. The radio type: pulse chirp.
2. Duration 320 us.
3. Law changes in frequency chirp: rising and falling.
4. Starting issue chirp after FROM: 350 us.
5. Frequency Deviation chirp: 400 kHz.
6. Center frequency chirped: 23,973 Mhz (41.713 ns).
7. Linearity deviation of not more than 2% or accuracy of at least ± 10 kHz.
8. Frequency clock oscillator: 38.3568 Mhz (Tti = 26.0709 ns).

Structurally, the core module 'LCM' (see diagram) includes the following blocks:

1. Generator NTI predetermined duration position for phase accumulator.
2. RS-TRIGGER delay circuit to activate and reset sequence chirp.
3. Delay circuit chirp sequence from the beginning of the trigger pulse DIV-SUM.
4. Reversing asynchronous counter with preset coefficients division.
5. Switches division factors counter.
6. Drive multi-bit phase accumulator and register.
7. Scheme permit issuance chirp to "2-AND".

DESCRIPTION OF WORK

On arrival of the trigger pulse (IZ) resets the prescaler clock frequency 38.3568 MHz on the counter and shaper meander on asynchronous D-flip-flop divider by two. Also from resets phase accumulator register and the activation of RS-trigger, thereby activating the circuit operation delay generated chirp sequence. Instantaneous frequency of the chirp signal is constructed on the basis of the phase accumulator is determined by the formula 1:

Flcm = Klcm * Fti / 2^N (1)

where:
Fti - clock frequency,
N - bit adder.

Minimum bit phase accumulator to ensure the accuracy of the conditions of formation of the output frequency is not less than ± 10 kHz:

N ~ Ft / ± 10 kHz ~ 38.3568 MHz / 10 kHz = 111 011 111 011 = 12. (2)

Ask a larger capacity equal to 16, the condition of overlap required accuracy, but it is more convenient to work with the bit drive a power of two.

Initial division ratio of the counter and taking into account the deviation of the center frequency of the chirp (formula 1):

K (LCM) 1 = Fmin * 2^16 / Fti = 23.77283 MHz * 2^16 / 38.3568 Mhz ~ 40618

The final division ratio of the counter and taking into account the deviation of the center frequency of the chirp is:

K (LCM) 1 = Fmax * 2^16 / Fti = 24.17257 MHz * 2^16 / 38.3568 Mhz ~ 41301

Frequency from Fmin to Fmax or vice versa must change for a time equal to the duration of a given chirped pulse Tlcm = 320 us. The counter counts down while DELTAK = K (LCM) 2 - K (LCM) 1 = 41301 - 40618 = 683 pulse generator NTI. Hence we can determine the period of the generator NTI:

Tnti = Tlcm / DELTAK = 320 us / 683 = 468.5 ns (3)

Overall coefficient generator prescaler NTI:

Ksum = Tnti / Tti = 468.5 ns / 26.0709 ns ~ 18. (4)

Work down counter is performed in two stages:
1. Upon the arrival of the trigger pulse FROM given permission for entry of CE, pre-activated recording division factor input L and is recorded on the front of the count input S.
2. When firing delay circuit chirp sequence enables the counter is activated and the output resolution on the chirp "2-I".

Income NTI clock counter begins to increase or decrease the output sequence for the phase accumulator, depending on the mode input UP counter. Upon reaching the coefficients K (LCM) 1 or K (LCM) 2 depending on the direction of the reverse - the counter and delay circuit RS-flip-flop are reset thereby disabling output enable chirp "2 AND". Switching conversion factors buferniki performed with Z-controlled state BUFT zero depending on the direction of translation (LFM mode decreasing or increasing).

FEATURES OF REALIZATION

1. To reduce crosstalk and interference, PCB layout should be done with a single continuous layer of metallization, locking ceramic containers about supply pins. All nazadeystvovannye custom pins I/O FPGA planted inside the ground and configured as outputs.
2. All counters and triggers asynchronous.

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