 Hello, and welcome to this presentation of the STM32MP1 series, External Memories Overview. This presentation quickly summarizes some key points for the selection of external memories and the related constraints for an application using STM32MP1 series devices. Let's start to see which kind of flash memories can be used with the STM32MP1 series. Flash memories are used to store code and or data. Due to high processing performance needed, accessing code and or data became a bottleneck, and an intermediate workspace like an external DDR is always required. In an operating system environment, the flash memory is managed as a file system, so execute in place or XIP is not possible, and the flash memory always needs a specific driver tailored to each particular device. In most systems, there is more than one flash to cope with the strength or weakness of each type of flash technology, or to separate storage to increase performance, security, or user flexibility. This table summarizes most of the differences between the various flash technologies, which can be used in an STM32MP1 microprocessor system. Serial NOR flash technology has a very good PCB area, due to low pin count of serial devices and very good reliability. The cost of high density and the right performances are the bottleneck to use NOR flash memories for large storage. Serial NAND flash technology has a very good PCB area and better cost and right performances than Serial NOR flash technology. Reliability is often seen as lower than for Serial NOR flash technology, but error correction is embedded in the hardware and transparent to the file system. Raw NAND technology has a parallel interface, which is not good for PCB areas, but offers a good trade-off between cost and performance. Most raw NAND memories do not have an embedded error correction, and so need additional hardware and file system management for bad block management and wear leveling. EMMC devices are widely used in the mobile phone market, and so offer very good price and performance. EMMC memories embed error correction, as well as fully automatic bad block management and wear leveling. Removable devices such as SD card or USB stick are providing very good cost at large density, but at the expense of lower flexibility and reliability due to user access and mechanical constraints. STM32 MP1 series can interface Serial NOR and Serial NAND memory interfaces through the Quad SPI interface, which can support up to two 4-bit devices. STM32 MP15 series can only boot from the first Quad SPI device. Raw NAND memories can be connected to the flexible memory controller or FMC. The possible configurations are either one 8-bit or 16-bit device or two 8-bit devices sharing the same data bus. Only SLC device requiring up to 8-bits ECC are supported. STM32 MP1 series can boot from Raw NAND memory devices. EMMC memories can be connected to any of the SDMMC interfaces. SDMMC3 has only four data bits. EMMC devices support one 4 or 8 out-bit data width. STM32 MP15 series can boot from EMMC memory connected to the SDMMC2 interface. SD card can be connected to any of the SDMMC interfaces. STM32 MP15 series provides optional control for external level shifter, mandatory for the support of UHSI mode, which requires 3 volts, then 1.8 volts signaling. The STM32 MP1 series can boot from an SD card connected to the SDMMC1 interface. This slide shows the usual flash density available by technology. Note that a flash memory with a size less than 1 gigabit, 128 megabytes, cannot be used alone. As such, size does not allow the storage of the operating system, but can store data anyway when used in conjunction with another larger flash holding the operating system itself. Let's continue with DRAM memories supported by the STM32 MP1 series. Here are some fundamentals about the DRAM technology. Despite their inherent complexity and constraints, dynamic RAMs are used in many devices, as it is the only memory available with a very large density at an affordable price. DDR3 technology has been superseded by DDR3 L technology, which offers the same performance but consumes less power. LP DDR2 technology offers smaller packages and less signals on PCB than the DDR3 DD3L1, a better power consumption, but usually has a higher price and needs two different supply voltages. The STM32 MP1 series support DDR3 or DDR3L memory devices in either 16-bit or 32-bit interface configuration on some packages only. As neither DDR3 nor DDR3L memory devices exist with a 32-bit interface, this configuration requires two devices, which are using a great deal of PCB space. Package ball pitch is 0.8 mm, which is adapted to industrial robustness. LP DDR2 or LP DDR3 memory devices mostly exist in 32-bit versions and offer lower signal count than DDR3 DDR3L1s. The package is smaller, but the pitch can be 0.67 mm, 0.5 mm or below, requiring additional PCB cost. The STM32 MP1 series supports between 1 gigabit, 128 megabytes, and 8 gigabits, 1 gigabyte of DRAM memory. When designing a DDR system, DDR constraints must absolutely be taken into account. Refer to AN5031 and AN5122 for details. STM32 CubeMX provides a tool that helps tuning the DDR parameters and checking the DDR signal integrity directly on the final target. More details are provided in the ecosystem training part. All related DDR specifications are standardized through JEDEC. The key points to remember from this presentation are the STM32 MP1 series always needs an external flash memory device. External DRAM, such as DDR3 DDR3L or LP DDR2 LP DDR3 devices, require a careful PCB design and signal integrity analysis. And STM32 CubeMX helps to configure and validate the DDR memory on the final target. The recommended flash or STRAM size depends on the operating system configuration. In addition to product data sheet and reference manual, these two application notes are recommended before any design phase using the STM32 MP1 microprocessor.