 The 14th lecture and we are going to do mid-band analysis of FET amplifier, so far we have been concerned with PjT and PjT we discussed the CE connection, the CB connection, common base and the CC connection, common collector or the emitter follower and we shall see that FET amplifiers are very similar in analysis and performance characteristics, for example CE is comparable to common source CS, emitter terminal is comparable to the source terminal, common base is comparable to CG, common gate and common collector is comparable to common drain. Now what are these characteristics, if I take the voltage gain AV that is the same for CE and CB that is gm minus no there is a difference, there is a difference of phase, in CE there is an inversion in CB there is no inversion but the gain magnitude is the same gm times rl parallel rc, okay. However if CE is unbypassed RE, CE with unbypassed RE then the gain drops down drastically agreed, with unbypassed emitter resistance the gain drops down drastically whereas for CC AV the voltage gain is less than 1 but very close to unity, very close to unity. These characteristics as you shall see will be the same if E is substituted by S, B is substituted by G in the case of the FET amplifier. As far as the input resistance is concerned the lowest input resistance is for which connection, CB common base connection it is the lowest for CE it is moderate and CE with RE unbypassed, how do I indicate this let us put CE equal to 0 that indicates that RE is unbypassed and CC the input resistance is very high, it is of the order of rpi plus beta plus 1 times RE. The current gain, current gain is high for CE and CC but it is less than 1 for common base CB as far as r0 is concerned which as far as r0 is concerned which configuration has the lowest r0, common collector and the r0 is of the order of 1 over gm. For the other 2 configurations they are approximately equal to r sub, yes? C, for CE and CB and whatever we have said so far about common emitter also applies to common source, common base also applies to common gate and common collector also applies to common drain. Of the 3 configurations the most generally used configuration is the common emitter, common emitter is a general purpose configuration because it has moderate voltage gain, moderate current gain, its input impedance is neither very large nor very low, output impedance is of the order of r sub C so it is at your choice, this is the most commonly used. In FET, in FET it would be the common source, okay, most commonly used. Now there are 2 special uses of the common base, one special use for common base, one special use for common collector. What is used for common base? If you are driving, if your signal source is high impedance then you apply to a common base because the input impedance is low. On the other hand if your signal source, if your signal source is high impedance v s, r s, okay then you apply to a common base so that it is a current drive basically, a source having high impedance is a current source, okay, more than a voltage source. So it is apt to apply a common base circuit whereas a common collector circuit is used where the source is a voltage source that is input impedance is low, okay and the common collector circuit the other use is that it acts as a buffer from a high impedance source to a low impedance load, okay. In the tutorial class today, during this week there is a problem of, there is a problem that is given for matching a source to a load, all right. The source impedance is 1000 ohms and the load impedance is 50 ohms. Obviously if we connect this directly, if we connect the source to the load directly there is heavy mismatch. So if you want to deliver maximum power to the load then what you do is you insert an amplifier in between such that the input impedance is 1000 ohms and the output impedance is 50 ohms, okay. So this is the problem of matching and an amplifier can very well fit the purpose. The problem you shall do yourself. Now let us take an FET amplifier. The basic equivalent circuit, AC equivalent circuit that we shall use for an FET, this is the gate, this is the drain, this is the source. Basic equivalent circuit would be the gate is open, this is the source, this voltage is V GS, V GS the phasor voltage and then you have a current generator, g m times V GS, g m times V GS and it is paralleled by a dynamic drain resistance R sub D which occurs due to non-parallel nature of the characteristics with respect to the voltage axis. If you draw the FET characteristics these are not perfectly parallel but they are slightly inclined and this slight inclination and the BJT this was called early effect in the FET there is no special name for it but there is a voltage comparable to the early voltage and for reasons to be made clear in another course this is denoted by lambda inverse, okay lambda inverse is comparable CF V sub A the early voltage in BJT, it is for peculiar reasons it is called lambda inverse, okay and R sub D you can find from the characteristics you find the slope, okay that is extend this on the negative axis and find out where it cuts and that voltage divided by the current well you can do that way or if lambda inverse is given then R sub D is given by lambda inverse divided by I sub D the drain current in the previous case it was V A divided by I sub C, okay very comparable, very much comparable R D is the dynamic drain resistance as far as G M is concerned G M can no longer be calculated by a simple formula like the one that you had used that is I sub C divided by 26 no no longer that because your drain current I sub D is not a linear relationship it is a relationship like this it is a square law 1 minus V G S divided by V P whole squared where V P will be replaced by V T if it is an enhancement mode MOS at T and G M has to be found out as D I D, D V G S at the operating point at the operating point and you can see that this is twice I D S S divided by minus V P times 1 minus V G S divided by V P do you notice that I have changed the total voltage to the DC voltage because you shall have to find this G M at the operating point and every time you shall have to find this therefore for the transistor that is specified you must be given V P the pinch of voltage or V T the threshold voltage we shall see how these are calculated when you take an example. Now the analysis is very routine and very similar to what we have done for V J T so we will go a little hardedly not quite hardedly we will omit some of the algebraic steps okay I will simply say this is how the equation is written and you simplify and find out the result alright this but as far as you are concerned I suggest that you do it yourself very carefully first a common source amplifier you have a V D D and the usual story R sub D you have the I am drawing the J I am drawing the F E T always as a JFET but it should be clear that the same circuit applies to MOS F E T also only the symbol shall differ okay I will for simplicity I will draw it like this okay this is the source and the source as you know is connected for biasing reasons is connected to a resistance R sigma and you know why sigma was used because R S is reserved for source resistance alright and as usual R sigma has to be bypassed by a C sigma alright has to be bypassed the output is taken from the drain through a coupling capacitor C 2 and you go to a load R L the voltage across R L is the output voltage V 0 and the current in R L is the output current I 0 as far as the what is the nature of the channel for the F E T that I have drawn N channel therefore what I need is a biasing through R 1 and R 2 the usual story however I want V G S to be positive or negative negative I want V G S to be negative therefore V G must be less than V S alright we will see how this is done then you have the coupling capacitor C 1 and the source R S and the source voltage V S once again it is the phasor this is the common common source F E T amplifier alright the equivalent circuit AC equivalent circuit can be drawn step by step you start with R S V S C 1 is a short R 1 and R 2 in parallel shall give you a resistance of we call this R G R G is equal to R 1 parallel R 2 okay and the gate is now open alright the gate is now open the source is shorted to ground as far as AC is concerned the short source is shorted to ground so the only other terminal that you need is the drain and the drain has a current generator G M V G S no I should write small G small S V G S is this voltage which is also equal to V I in our usual time analogy the actual voltage that is applied to the gate between the gate and ground okay so V I is equal to V G S G M V G S then we have the drain dynamic drain resistance R sub D and the two resistances capital R D and capital R L it is this voltage which is the output voltage and the current through R L is the output current I 0 it is very easy to see that the gain because V G S is the same as V I V 0 by V I shall be simply minus G M because this current does not agree voltage times R D parallel R D parallel R L that is it very simple the voltage gain and usually small R D is a very large quantity small R D is a very large quantity and therefore the gain is approximately approximately minus G M R D parallel R L if you so desire you can denote this resistance by R L prime as we did in the BJT K also looking at the circuit itself you can see that the input resistance R I is simply equal to R G no complication no R Pi no R X no no forward feedback so R I equal to R G and what about R 0 if you look from here if you look from here it is simply the parallel combination of R D parallel R D because the current generator is a 0 current generator and it has internal impedance of infinity 0 because V S is 0 then V I shall be equal to 0 alright and therefore we have found out the gain and the two impedances by inspection the only thing that remains to find out is A I which is the current gain is given by A V times R I by R L and it is very easy to see what this expression would be this would be equal to A V would be equal to minus G M R D R G divided by R D plus R G is that correct R L that is correct this should be R L no numerator R L cancels out because this is A I this is A I I beg your pardon this is A I now it is correct fine so okay we take an example see analysis is very simple it is much simpler than BJT why because the gate is isolated from the source and the drain okay gate is gate does not have a forward feedback part so the analysis is very simple and it can be done by inspection let us take an example we have a common source FET amplifier with please please look at this carefully IDSS the calculations are a little complicated more involved than BJT because of the trouble of finding G M okay and because V G S is V G minus V S you have to make sure that V G S is negative you have to make sure that V D S greater than V G S plus V P minus or plus minus V P all right so you have to make all these things otherwise the transistor will not work as an amplifier all these checks were not needed as long as the Q point is found out in a BJT the Q point which is reasonably good Q point you have to you have to worry about nothing else in an FET you do have to let us see IDSS is 10 milliampere given V P is given as minus 5 volt V D D is 15 volt plus 15 R 1 is 1 meg R 2 is 150 K and R Sigma is equal to R D is equal to R L all these three resistors are equal and values 15 K all right the question is to find the Q point and also the values of A V R I R 0 and A I these are the things to be found out in the common source amplifier now the first thing we do is to find out the drain current the Q point drain current and you know the drain current I D is IDSS that is 10 milliampere 1 minus V G S divided by V P so it will be 1 plus V G S divided by 5 whole square milliampere is that clear because V P is minus 5 the sign has become positive okay also you see V G S is equal to V G minus V S what is V G V G is V G G V G is V G G minus R Sigma times ID therefore V G S what is V G G this is 15 multiplied by R 2 that is 150 K divided by 1 meg plus 150 K minus R Sigma is 15 K times ID substitute this substitute this here then you get an equation in ID which is not a linear equation which is a quadratic and the equation after you clear the algebra and solve it okay I will skip all this arithmetic you get I sub D equal to 0.4 milliampere now quadratic has 2 solutions you must be careful in choosing the solution the other solution will make the FET not operate in the linear region alright the other solution will not be acceptable therefore V G S if ID is 0.4 milliampere you get V G S as 1.96 minus 15 K this is V G G incidentally which is also equal to V G 15 K multiplied by 0.4 milliampere this is 6 volt and therefore V G S is minus 4.04 volt and under this condition V G S is V D D that is 15 minus 0.4 milliampere multiplied by R D plus R Sigma that means 30 K alright 15 plus 15 and this comes out as 3 volt 3 volt and 0.4 milliampere is the Q point finally you have to check whether this V D S is greater than V G S minus V P obviously it is so okay alright that you check yourself. Now the other thing that remains to be found out is GM and R D it is given that lambda inverse for this no R D is given I will take a lambda inverse case later R D is given as 100 K how do you find GM? GM is twice ID SS divided by minus V P then 1 minus V G S upon V P everything is known you can substitute the values and get GM as equal to 0.8 milliampere be careful in this calculation and then once you have found this out the other things are simply putting down in the formula or just looking at the circuit you can write down the equation by looking at the circuit AV would be minus GM that is 0.8 milliampere parallel combination of 100 K 15 K and 15 K R D R L small R subscript small D and this comes out as minus 5.6 low gain R sub I which is R G is 1 meg parallel 150 K and this comes as 130 K R 0 would be if you take small R D into account 100 K parallel 15 K and this becomes 13 K alright. Now let us complicate matters is there any question on this? No if I can proceed at this rate we will be in good business. Yes sir, when you have a resistance R D? Yes sir won't that change the equation for ID sir won't it consist of R D also? No I don't find it. Small R D? Yes sir. Small R D comes only in the AC equivalent circuit not in the DC small R D comes only in the AC equivalent circuit it does not affect the bias. We next consider we next complicate matters let us put C sigma equal to 0 that is an unbypassed unbypassed source resistance. Now what will we do? Yes Sir we have not found the current gain. We have not found the current gain oh that is to that. A sub I is A V that is minus 5.6 multiplied by R I R I is 130 K divided by R L is 15 K you calculate what this value okay. So let us consider a C S amplifier with C sigma equal to 0 and all that you have to do now is to draw the equivalent circuit carefully and that solves the problem as we shall see. The equivalent circuit if we proceed in the usual manner V S R S then we shall have R G the same uhh same circuit this is the gate then since the source is not bypassed we must include R sigma agreed and this is the voltage which is V small G small S plus minus V G S no longer it is to ground no longer V G S equals to V I no V G S is not equal to V I agreed. Oh one thing that I did not calculate was A V S which you can very easily find out as A V multiplied by R I divided by R I plus R I that is very simple so I do not have to repeat that. Let me go to only procedures which are new then from the drain to the source we have G M V G S and to complicate matters there is an R R D we will see what happens when R D is included what happens when R D is not included and uhh I find it convenient to leave all complicated matters to students so including the effect of R D I will ask you to calculate yourself we will have occasion to to look at this and in this particular case in this particular example that we took R D cannot be ignored as you shall see in a in a moment but we shall do it we will we will make a rough calculation from the drain then we have the two resistances why did they change color? Two resistances R sub D and R sub L this is I 0 and this voltage is V 0 alright now you see look at the circuit it is said that if you can observe a problem carefully half of it is solved if you can observe this circuit carefully the calculations will be very simple G M V G S now no longer supplies only the parallel combination of R D and R L and small R D small R D is not parallel at all so this current source must supply two parallel paths one is R D small R subscript small D and the other is the parallel combination of R D R L and in series with R sigma okay if you recognize this fact then the calculation including the effect of R D shall be simple but we will find it convenient to ignore it it supplies you see across G M V G S there are two resistors one is R D and the other is R D parallel R L plus R sigma okay because these points are the same these points are the same they are all ground so what I had is R D parallel R L plus R sigma if you recommend this is the only single fact that has to be recognized to include the effect of R D now can we ignore the effect of R D in this case R D was given to be 100 K the parallel combination of R D and R L is 7.5 K and this is 15 so the parallel path is 22.5 K approximately one fifth of this path so the current shall divide into the same ratio one is to 5 is that clear Sir how does G M V G S divide parallel to R D? Oh there is a current source let me draw this G M V G S which is in parallel with small R D okay this point then we have R sigma plus R L prime therefore this current has two paths one is through this and the other is through isn't that right? This current after coming here where can it go? It has to flow like this and like this now if this path was very low resistance as compared to small R D we could have ignored small R D but the current now divides into approximately one is to 5 alright so we cannot ignore R D but we will make our calculation including excluding R D and leave R D effect to you so assume that R D is much greater than R sigma plus R D parallel R L okay we assume we derive our formula by assuming this if that is so then you see then you see that V 0 is simply minus G M V G S multiplied by R D parallel R L so all that request to be found out is V G S let us see what V G S is V G S is V G minus V S that is equal to V G is V I right V G is V I and V S is if we ignore small R subscript small D then G M V G S flows through R sigma therefore it would be simply G M V G S multiplied by R sigma okay this is an involved equation V G S occurs on the right side and also on the left side so you can find out V G S as equal to V I divided by 1 plus G M R sigma agreed this is how V G S has to be found out and once V G S is found out V 0 is minus G M V G S R D parallel R L and therefore the voltage gain S of V shall be equal to minus G M R D parallel R L divided by 1 plus G M R sigma what was G M in the previous example 0.8 millimaw and R sigma was 15 K so this is 12 is that right 12 is much large larger compared to 1 so approximately approximately the gain would be if G M R sigma is much greater than 1 then approximately the gain will be minus R D parallel R L divided by R sigma recall we had a similar formula in the case of a common emitter amplifier with unbypassed R E the gain was approximately negative of the ratio of the effective load to R E it is the same formula that applies here okay what is R I input resistance it is still equal to R sub G agreed and A sub I can be calculated as A V R I divided by R L in the usual manner you can write the expression what is R 0 if small R D is ignored then R 0 is simply capital R subscript capital D but if it is not ignored then complications arise and you have to solve a circuit let me indicate the circuit the solution would be left to you what we have to do is we have an R sigma then G M V G S okay G M V G S parallel R D R D and there is a resistance capital R subscript capital D you have to connect a voltage generator here and the current I 0 has to be found out R 0 would now be equal to V 0 by I 0 alright but what is V G S minus V S okay and what is minus V S this is minus what is the current flowing through this no V 0 it is R sigma multiplied by what is the current that is what we wanted to know in terms of I 0 V 0 if it is I 0 minus V 0 by R D that is correct alright so you know everything now in terms of I 0 and V 0 and therefore you can find out I V 0 by I 0 is the point clear no alright let me draw this resistance here R D then this current must flow through the R sigma this current after coming this current is I 0 minus V 0 by R D okay this current this current this one this current splits up into two parts one is to this one is to this they must combine here and flow through R sigma because a little bit of thinking but it is not difficult so you can find out V 0 by I 0 and I leave this to you whatever it is whatever this current is these two currents again combine here and flow through R sigma okay any question this is what we have found out G M V G S would be minus G M R sigma times I 0 minus V 0 by R D everything now in the circuit shall be in terms of I 0 and V 0 which current source right let me let me draw this circuit again now I shall draw in a different manner this would be minus G M R sigma I 0 minus V 0 by R D there is an R D here this is V 0 I 0 and this goes to R sigma alright so whatever current comes here whatever current comes here must flow here there is no other way and what is this current this is simply V 0 I 0 minus V 0 by R D this is what I have substituted for V G S V G S is minus R D minus R sigma multiplied by this current okay any other doubt I assure you this is correct I have not made any mistake yes or sure I have all the time in the world you must give me a signal when you are through we shall then consider the same example that we have considered for the C S amplifier which C sigma tends to what the previous example tends to infinity that is R sigma short circuit no I have not derived it therefore you have to derive it yourself consider the same example what was the example I D SS was 10 milliampere V P is minus 5 volt V D D is 15 volt R 1 is 1 meg R 2 150 K R sigma equal to R D equal to R L equal to 15 K small R D if it is 100 K then obviously all our calculations will be approximate okay nevertheless I give you small R D and I ask you to find what modification is needed we have already seen the modification in the calculation the output resistance all that you have to do is to split this current G M V G S that is about it okay so it should not be very difficult small R D is 100 K if you calculate will the DC will the Q point change no because everything is remain the same Q point does not change if Q point does not change G M does not change G M is the same G M is also then the same as 0.8 milli no and if you utilize these formulas then you get A V do not depend on formulas unnecessarily where you can see the formula C E rather than committing to memory okay if you if you calculate it is simply minus G M defective load divided by this divided by comes because C sigma is equal to 0 divided by 1 plus G M R 6 and that becomes minus 0.46 I will skip the arithmetic A sub I becomes minus 4 now you see A V the voltage gain now becomes less than 1 this is what the unbiased emitter source resistance does to the amplifier the current gain is minus 4 R I and R 0 are not changed they are the same as in the previous case okay done let us take the common gate amplifier you will see that the calculations are very similar there is no no difference except that you have to be a bit careful about the calculation of G M and the output resistance it is the output resistance which is the which is the complicated calculation now in a in a common gate amplifier C G which is equivalent to C B of BJT you have V S V S R S couple store a capacitor C 1 2 started on a wrong foot so let us change the page we have first let us draw the FET this is the source this is the gate and this is the drain now in order to bias these in order to bias the source we require a resistance R sigma and we cannot bypass it now we cannot bypass it in order to put a gate voltage we must have a resistance R sub 2 and we must supply it to the V D D okay from the drain we have the resistance R D this is R 1 and this should go to V D D plus V D D from here you take the coupling capacitor and take to the load R L the voltage is V 0 the current is I 0 and for reasons that I had stated in the case of the common base amplifier R 2 must be bypassed in other words there must be a capacitor here C C G okay there must be a capacitor here which bypasses R 2 to ground that R 2 is effective in DC in setting the DC operating point then your input is applied through a coupling capacitor and a source resistance R S and a voltage source V S and this goes to ground alright nothing will get a little little complicated because of R D small R subscript small D while it can be very easily ignored in a BJT you have to be careful in an FET as I said in the last analysis in the last example that it took our figures were varied up because small R D was not negligible compared to the parallel combination of R D R L and in series with R sigma okay that makes me happy now let us see what the equivalent circuit is we have R S V S AC equivalent circuit then you have the source node from which you have an R sigma and this voltage is V I okay this comes to from the source from the drain to the source the gate is common gate is grounded from the drain to the source you have the G M V G S what is V G S equal to minus V I is that clear this is the gate G so V G S is from this point to this point which is of opposite polarity to V I but magnitude is the same so I can write this is minus G M V I this is the simplification occurring immediately and then you have this inevitable nuisance of R sub D the drain the dynamic drain resistance and from here you have the capital R D and capital R L this is V 0 and this is I 0 okay the things are not too bad as far as the equivalent circuit is concerned because there are only 2 nodes not only that not only that since we are finding out the gain gain is a relationship between V 0 and V I you can write the node equation at D in terms of V I and V 0 nothing else as you can see node equation at D is V 0 G L now it is conductances it becomes simpler to do it that way G L plus G D plus okay V L G S G L plus G D then V 0 minus V I divided by R D so plus V 0 minus V I multiplied by small G subscript small D okay this is the current to R D then I have this extra term minus G M V I okay this is the node equation and the node equation contains only V 0 and V I why this I have to add this current this current and this current this current is G M V G S which is minus G M V I okay so since this equation contains only V 0 and V I it is very easy to find out the voltage gain and the expression is G D plus G M divided by G L plus G capital D plus small G subscript D and if R D could be ignored if it could be ignored wishful thinking it should have been approximately G M divided by G L plus G D do not you see that this is the same as G M R L parallel R D is this obvious 1 by G L plus G D conductances at so the 2 resistors are in parallel is also obvious from the equivalent circuit okay equivalent circuit never tells a lie if R D is ignored if it is infinity then this current has to flow through this and that is the voltage gain it is only because of R D that we have to write a node equation at the node D otherwise we do not have to okay if a big if G D is much less compared to G M as well as G L plus G D if this is true then this will be approximately the story if you want to find out the input resistance now the input resistance is also also complicated by the occurrence of R D okay and the occurrence of G M minus G M V I the input resistance is no longer R Sigma no okay to find the input resistance all I need is the ratio of V I to I I okay and therefore what I can do is I can write a node equation at the node S if I write that at the at the node S I I is coming G M V G S is coming G M V G S is minus G M V I this current will be going off V I by R Sigma and current through R D which is V 0 minus V I multiplied by G D okay now the complication is that in this node equation you have V 0 but you know what is V 0 by V I you have already calculated V 0 by V I and therefore it is not difficult the equation that we get is if you see it is V I divided by R Sigma is the current that is going minus this current leaves the current coming is G M V G S so this is G M minus V I is the current generator plus V I minus V 0 is the current going divided by R D divided by R D now what you do is you divide by V I then you get 1 by R I as equal to 1 by R Sigma plus G M then plus G D minus G D times A V that is right now you substitute for A V and simplify the expression that I get it is a bit of algebraic simplification not very not very complicated you get 1 by R I as equal to G Sigma plus G L plus G D this requires a bit of algebraic simplification as I said G M plus G D divided by G L plus I hope I am right G D plus small G D that is what I get and once again if your wish comes true that is if small G D is negligible compared to G M and G L plus G D do not you see that this is simply G Sigma plus G M agreed which means that R I is the parallel combination of R Sigma and what else 1 by G M okay let us let us see this R I is approximately the parallel combination of R Sigma and 1 by G M in the example that we took what was what was I am sorry I made the mistake because someone look back do not look back R Sigma parallel 1 by G M okay what was R Sigma in our example 15 K and 1 by G M 1 by 0.8 K which is 1 point 1.25 do not you see that R Sigma is large compared to this and therefore this is approximately equal to 1 by G M if you recall in the common base amplifier this was exactly the same story except that 1 by G M is now not as small as 25 ohms in the previous case it was some 25, 24 or 25 ohms this is now 1.25 K this is the general story alright and finally finally of course A I can be calculated from A V R I divided by R L you find out the expression but I can mention that under this condition small R subscript small D very large this is approximately R D divided by R D plus R L so the gain is current gain is less than 1 it has to be in a common base case this was also true as far as capital R 0 is concerned the output resistance is approximately equal to R D if small R D goes to infinity if this is not the case then I am afraid you have to calculate this from this equivalent circuit R S R Sigma R D G M V G S where is V G S now V G S occurs across R Sigma and with what polarity minus up and plus down agreed so this is V G S this is G M V G S it is not difficult to calculate then you have an R D and I 0 and V 0 please do carry out these calculations okay and find out what is R 0 how does R D effect a check on this calculation would be that if you put R D equal to infinity the value should be capital R D that would be the check and this is a good point to stop next time that is Thursday we will work out some problems and we will also look very briefly at the common what is remaining common drain not collect common drain FET amplifier rolling is the process of producing different components by plastic deformation of work material by passing it between rotating rolls the process is called longitudinal rolling if the forming rolls are rotating in the opposite directions and flow of work material is along the length of the jaw and perpendicular to the central line of the rolls by this process we can produce products like bars of different cross sections steel for constructional work flat products like plates and sheets of various thickness can also be produced by this process another version or type of rolling process is transverse rolling let us have a look at a transverse cold rolling machine in this process the forming rolls are rotating in the same direction and the flow of material is either radial