 Hello and welcome to this presentation of the STM32 System Window Watchdog. It will cover the main features of this peripheral used to detect software faults. The Window Watchdog is used to detect the occurrence of software faults. The Window Watchdog can be programmed to detect abnormally late or early application behavior. It is best suited for applications required to react within an accurate timing window. Once enabled, it can only be disabled by a device reset. An early wake-up interrupt can be generated before a reset happens to perform a system recovery or manage certain actions before a system restart. The Window Watchdog offers several features. The user can program the timeout value and the window width according to application needs. It can generate a reset under two conditions. When the down counter value becomes less or equal to 0x3f or when the Watchdog is refreshed outside the time window. It can generate an early wake-up interrupt when the down counter reaches 0x40. The early wake-up interrupt can be used to reload the down counter in order to avoid a reset generation or to manage system recovery and context backup operations. As shown in the figure, the Window Watchdog uses the APB clock, or PCLK, as reference clock for its time base. The PCLK is provided by the RCC block. This clock is divided by 4096 and by a value programmed by the application. The application can also program the reload value of the down counter bits T6 to 0. The window width is controlled by bits W, 6 to 0. The STM32H7 includes two Window Watchdogs, WWDG1 and WWDG2. WWDG1 is dedicated to CPU1 usage and the WWDG2 is dedicated to CPU2 usage. WWDG1 is connected to the APB3 bus of the D1 domain. WWDG2 is connected to the AP1 bus of the D2 domain. The WWDG1 early interrupt output is connected to the NVIC of the CPU1 but also to the EXTI in order to wake up and interrupt the CPU2 if the application requires such a feature. In the same way, the WWDG2 early interrupt output is connected to the NVIC of the CPU2 but also to the EXTI in order to wake up and interrupt the CPU1 if the application requires such a feature. For each Window Watchdog, it is possible to select if the Watchdog will freeze when the associated CPU is in debug or core halted mode. Please refer to the microcontroller debug unit or DBGMCU description for details. The Window Watchdogs are frozen when the system is in stop or standby mode but can remain active when the corresponding CPU is in C sleep mode. Both Watchdogs have the capability to perform a system reset handled by the RCC block. This diagram illustrates how the Window Watchdog operates. When the 7-bit down counter rolls over from 0x40 to 0x3F, it initiates a reset. This happens if the application software does not refresh the Window Watchdog on time. The early interrupt, if enabled, can be generated when the down counter reaches 0x40. If the software refreshes the Watchdog while the down counter is greater than the value stored in bits W, 6-0, a reset is generated. This happens when the application refreshes the Watchdog too early. No interrupt is generated in this case. To prevent a Window Watchdog reset, the Watchdog refresh must happen while the down counter value is lower than the time value window and greater than 0x3F. This is illustrated by the green area. The refresh operation consists on reloading the down counter with bits T, 6-0. To enable the Window Watchdog clock, the corresponding Window Watchdog enabled bit in the RCC block must be set to 1. Note that once the APB clock for the Watchdog is enabled, the application cannot disable it. Only a system reset can disable the Watchdog clock. A low power enabled bit can be set as well if the application wishes to keep the Window Watchdog activated even if the CPU is in sleep mode. The down counter uses the APB clock PCLK divided by 4096 and again divided by a division ratio selected by the application. It can be 1, 2, 4, 8, 16, 32, 64 or 128 as defined in the WWDG CFR register. The formula shown in this slide lets you determine the Watchdog timeout value. When a system reset occurs, it is possible to identify which parts cause the reset thanks to status flags provided by the RCC block. The Window Watchdogs can be one of the sources. The early wake-up interrupt can be used in order to perform emergency tasks before the reset occurs, such as data logging, data protection, Watchdog refresh in order to prevent the reset or other emergency tasks. The EWI interrupt occurs whenever the down counter value reaches 0x40. It is enabled by setting the EWI bit in the WWDG CFR register. The EWI interrupt is cleared by writing 0 to the EWIF bit in the WWDG SR register. The Window Watchdog is active in run and sleep modes. It is not available in stop or standby modes. In sleep mode, the Window Watchdog clock can be disabled by clearing the corresponding low power enable bit located in the RCC block.