 Hello, and welcome to this presentation of the STM32i2C interface. It covers the main features of this communication interface, which is widely used to connect devices such as microcontrollers, sensors, and serial interface memories. The I2C interface is compliant with the NXP I2C bus specification and user manual revision 3. The SM bus system management bus specification, revision 3, and the PM bus power system management protocol specification, revision 1.3. This peripheral provides an easy to use interface with very simple software programming and full timing flexibility. Additionally, the I2C peripheral is functional in some low power stop modes. The I2C peripheral supports multi-master and slave modes. The I2C IO pins must be configured in open drain mode. The logic high level is driven by an external pull-up. The IO pins support the 20 milliamp output drive required for fast mode plus. The peripheral controls all I2C bus specific sequencing, protocol, arbitration, and timing values. 7 and 10-bit addressing modes are supported, and multiple 7-bit addresses can be supported in the same application. The peripheral in master mode supports slave clock stretching and clock stretching from slave side. In slave mode configuration of the peripheral, the clock stretching can be disabled by software. The setup and hold times are programmable by software. Analog and digital glitch filters on the data and clock lines can be configured by software. The peripheral can wake up the MCU from stop mode when an address match is detected. The peripheral has an independent clock domain, which allows a communication baud rate independent from the system clock. Here is the I2C block diagram. The registers are accessed through the APB bus, and the peripheral is clocked with the I2C clock, which is independent from the APB clock. The I2C clock can be selected from among the PLL, APB clock, the high-speed internal RC oscillator with a frequency from 8 to 64 MHz, and the low-power internal 4 MHz RC oscillator. Analog and digital noise filters are present on the SCL and SDA lines. A 20 mA driving capability is enabled using the control bits in the system configuration registers. In addition, an SM bus alert pin is available in SM bus mode. The I2C setup and hold times can be configured by software through the I2C timing register. The SDA DEL and SCL DEL counters are used during transmission in order to guarantee the minimum data hold and data setup times. The I2C peripheral waits for the programmed data hold time after detecting a falling edge on the clock line before sending the data. After the data is sent, the clock line is stretched low during the programmed data setup time. The total data hold time is greater than the programmed SDA DEL counter. This is due to the fact that SDA DEL delay is only added once the SCL falling edge is internally detected. The time or T-SYNC 1 needed for this internal detection depends on the SCL falling edge, the input delay due to the filters and the delay due to the internal SCL synchronization with the I2C clock. However, the setup time is not impacted by these internal delays. The I2C master clock's low and high level durations are configured by software in the I2C timings register. The SCL low and high level counters start after the detection of the edge of the SCL line. This implementation allows the peripheral to support the master clock synchronization mechanism in a multi master environment as well as the slave clock stretching feature. Therefore, the total SCL period is greater than the sum of the counters. This is linked to the added delays due to the internal detection of the SCL line edge. These delays, T-SYNC 1 and T-SYNC 2 depend on the SCL falling or rising edge, the input delay due to the filters and the delay due to the internal SCL synchronization with the I2C clock. The rising edge depends on pull-up resistor and SCL line capacitance. The falling edge depends on the IOPORT parameters defined in the datasheet. In order to properly configure clock speed, these edges can be either measured or calculated. They are needed in order to properly configure the I2C peripheral in the STM32 QBMX tool. Then the settings of the timing register can be automatically calculated by this tool. The I2C slave can acknowledge several slave addresses. The slave addresses are programmed into two registers. Own address register 1 can be programmed with a 7 or 10-bit address. Own address register 2 can be programmed with a 7-bit address, but the least significant bits of this address can be masked through the OA2 MSK register in order to acknowledge multiple slave addresses. The two own address registers can be enabled simultaneously. The I2C peripheral supports wake-up from stop mode on address matches. To do this, the I2C peripheral clock must be set to the HSI or CSI oscillator. Only the analog noise filter is supported when the wake-up from stop feature is enabled. All addressing modes are supported. When the device is in stop mode, the high-speed internal oscillator is switched off. When a start condition is detected, the I2C peripheral enables the high-speed internal oscillator, which is used to receive the address on the bus. After an address is received in stop mode, a wake-up interrupt is generated if the address matches the programmed slave address. If the address does not match, the high-speed internal oscillator is switched off, no interrupt is generated, and the device remains in stop mode. Clock stretching must be enabled because the I2C peripheral stretches the clock line low after the start condition until the high-speed internal oscillator is started. After having received an address that matches the programmed slave address, the I2C peripheral also stretches the clock line low until the STM32MP1 device is awakened. Master mode software management is very simple. Only one write action is needed to handle a master transfer with a payload smaller than 255 bytes. The full protocol is managed by the hardware. In order to start a transfer in master mode, I2C control register 2 must be written with the start condition request, the slave address, the transfer direction, the number of bytes to be transferred, and the end of transfer mode. End of transfer mode is configured by the auto-end bit. If it is set, the stop condition is automatically sent after the programmed number of bytes is transferred. If the auto-end bit is not set, the end of transfer is managed by software. After the programmed number of bytes is transferred, the transfer complete or TC flag is set and an interrupt is generated, if enabled. Then a repeated start or a stop condition can be requested by software. The data transfer can be managed by interrupts or by the DMA. When the payload is greater than 255 bytes, the reload bit must be set in I2C control register 2. In this case, the transfer complete reload or TCR flag is set after the programmed number of bytes has been transferred. The additional number of bytes to be transferred is programmed when the TCR bit is set and then the data transfer will resume. The I2C clock is stretched low as long as the TCR bit is set. The reload bit is used in master mode when the payload is greater than 255 bytes and the in slave mode when slave byte control is enabled. When the reload bit is set, the auto-end bit has no effect. By default, the I2C slave uses clock stretching. The clock stretching feature can be disabled by software. In receive mode, the slave acknowledge on received byte behavior can be configured when slave byte control mode is selected together with the reload bit being set. When the SBC bit is set, the number of bytes counter is enabled in slave mode. Clock stretching must be enabled when slave byte control is enabled. In receive mode, when slave byte control is enabled with the reload bit set and the number of bytes to be transferred is 1, the transfer complete reload flag is set after each received byte and the SCL line is stretched. This is done after data reception and before the acknowledge pulse. The receive buffer not empty flag is also set so the data can be read. In the TCR subroutine, an acknowledge or not acknowledge can be programmed to be sent after the byte is received. It is recommended to clear the SBC bit in transmission as there is no use for the byte counter in I2C slave transmitter mode. In SM bus mode, slave byte control mode is used in transmission for sending the PEC or packet error code byte. The I2C peripheral provides hardware support for the SM bus. The SM bus address resolution protocol is supported through the device default address and arbitration in slave mode. The host notify protocol is supported with host address support. The alert protocol is supported through the SM bus alert pin and alert response address. The SM bus clock low timeout and cumulative clock low extend times can be detected with a programmable duration. The bus idle condition can be detected with a programmable duration. Command and data acknowledge control is supported through slave byte control mode. The packet error code or PEC byte is calculated by hardware. The packet error code or PEC byte is automatically sent in transmission and checked in reception. The data transfer counter initialized with the N bytes value is used to automatically check the PEC byte in reception after N bytes minus 1 byte are received. If the receive PEC byte does not match the calculation, a not acknowledge is automatically sent after the PEC byte. In transmission, the internally calculated PEC byte is automatically sent after N bytes minus 1 byte. Slave byte control mode must be enabled in slave mode in order to enable the N bytes counter and allow automatic PEC reception or transmission. Several events can trigger and interrupt. The receive buffer not empty flag is set when the receive buffer contains received data and is ready to be read. The transmit buffer interrupt status is set when the transmit buffer is empty and is ready to be written. The stop detection flag is set when a stop condition is detected on the bus. The transfer complete reload flag is set when the reload bit is set and N bytes bytes of data have been transferred. The transfer complete flag is set when the reload and auto end bits are cleared and N bytes bytes of data have been transferred. The address match flag is set when the received slave address matches one of the enabled slave addresses. The NACK reception flag is set when a not acknowledged is received after a byte transmission. DMA requests can be generated when the received buffer not empty or transmit buffer empty flag is set. Several error flags can be generated. A bus error detection flag is set when a misplaced start or stop condition is detected. The arbitration loss flag is set in the event of an arbitration loss. An overrun or underrun error flag is set in slave mode with clock stretching disabled when an overrun or an underrun error is detected. In SM bus mode, a PC error flag is set when the received PEC does not match the calculated PEC register content. A timeout error flag is set when a timeout or extended clock timeout is detected. An alert pin detection flag is set in the SM bus host configuration when alert is enabled and a falling edge is detected on the SMBA pin. Here is an overview of the I2C instance status in specific low power modes. This status depends on state of MPU or MCU subsystem domains and to which of them the peripheral instance is allocated. The I2C peripheral is active in C run and C sleep modes. In stop and LP stop modes, the peripheral registers content is kept and if the I2C peripheral is clocked by HSI or CSI clock, the address recognition is functional. The I2C address match condition causes the device to exit stop mode. In LPLV stop mode, the peripheral is no more functional but the registers content is kept. In standby mode, the peripheral is powered down and must be reinitialized after exiting standby mode. For each I2C peripheral, a bit is available for debugging purposes and debug component that can be used to stop the SM bus timeout counter when the core is halted. STM32MP1 microcontrollers embed six I2C peripherals all with the same set of features. I2C1, I2C2, I2C3 and I2C5 can be controlled by the Cortex-M4 core either directly or through DMA1 or two but it can also be managed by the Cortex-A7 CPU subsystem as well. I2C4 and I2C6 are secure communication blocks dedicated to the Cortex-A7 core. For more information related to this peripheral, you can also refer to these trainings. System configuration controller, reset and clock controller, power controller, interrupts controller, and direct memory access controller. For more details, please refer to the I2C bus specification and user manual from the NXP website. The SM bus specification can be found in the smart battery system implementers forum. The PM bus power system management protocol specification can be found in the power management bus implementers forum.