 We're now at the presentation with tools for kids. So I'm now going to talk about tools for engineers. So A6, and A6 is a four-letter word for application-specific integrated circuit. But it actually is a broader meaning or a changed meaning, so you just use it. By the way, I also want to thank Wayne, because I normally had a Pira. I was on the list for the Pira, which is a follow-up of Pandora to present yet, but it's not ready yet. So I borrowed Wayne's. So you can consider this talk as sponsored by Ticat. So, and I'm working at iMac. We do support services for making A6. So that's why I'm in the business. And I think I'm looking, can we make it feasible to make an A6 with open source tools? And can you pay for it? So this is an overview. I first want to say that probably also chips want to be free. So you know, 20 years ago, when the movement started, when FOSM started, all these things, they talked about information wants to be free, so I also think chips want to be free. So I want to discuss my dream, and then how I'm trying to achieve it. And then I will focus on the tool chain here in this talk to see what is the status. So you know, 20 years ago, people started the Linux movement, which one of the big contributors to the open source movement, and their people could just hack at night at their PC and Linux, for example, and all the people that just could do a lot of things. But up to now, you cannot do that for A6. So custom A6 have highest startup cost, but now maybe time of shift, you have crowdfunding, so you can share things. So maybe if you have some startup cost, you can share them by crowdfunding. And you can do distributed development through GitHub and GitLab and these kind of things. So I have a dream. So what is my dream? My dream is to be able to do for low volume open source A6 service. If you look at normal A6 production, they target high volume, so they have high startup costs, but low per unit costs. And you have to earn back your startup costs with selling a lot of products. And these startup costs are mass costs, the tools you use to do the chips. The engineers who work in it, they also want to get paid and have food on the table. Also the IP blocks themselves, you will need to pay. And also the first thing, before people want to talk to you, the first thing you have to do is sign in the A or so. So that's also not very open source friendly. So what I want to target is a service where you could have products made. So I mean full boards with less than 100 euros. If you order around 100 boards, and if you go in volume, then probably the prices will drop a lot. So how to achieve that? First, we need an open source RTL to layout flow. So not try to reinvent or repay for the wheel. So the IP blocks also. Hopefully, we can pool then also making the chips. So people already do that for wafers. But like I said, the fine print is often not easy for a normal guy to do. You also need the EDA flow, which is push button so that people who write RTL code are mainly experts and you need a lot of time. And that should be, you should try not to have too much time to get into the flow. And also, somebody should be in between the real foundry so that he can see that everything legally is OK and that the guy who writes the code doesn't have to take care of it. So I'm doing a pilot project. It's a crowdfunded project. And the purpose of that is to find out, to get the first set of reusable cores, to test the flow, investigate where all the startup costs are, where we can do the reduction, and also look at what is from legal side needed or wanted by the foundries. And this is the retro microcontroller, I call it. It has a Z80 core, a MOS 6502, and a Motorola 68 cows on it. But I'm not going to detail in this one that I will talk next tomorrow in the retrocuban death room where I will detail this part. I'm just now focusing on my experience I have with the toolchain, the open source toolchain. So what is an ASIC toolchain is that you have RTL code that you develop. This is layout sign off production test product. I will go in detail further. So let's first discuss. We have seen FPGAs in a few previous presentations. And there also Tristan already covered it. You have the fixed programmable blocks. So you have a fixed thing. And then you program the logic blocks or the layout blocks and interconnects. But an ASIC is made with what they call standard cells. So each standard cell has a certain functionality. This is a NAND gate and half adder and a flip flop. And then you assemble a lot of these on a chip and you make a chip out of that. So that's the ASIC flow. And you can understand that the tools that you need to use for an ASIC flow are different than for an FPGA flow. For up to the logic part, RTL development simulation, these are similar. But from then on, it starts to become different. So what are the tools you need? For RTL development, you have to type in your code. You want to simulate it. Maybe you verify it on FPGA. Even formal verification, people are working on that now. Synthesis is actually your RTL code, which is event-driven code that you then transform into a net list of the standard cells. That's what's called synthesis. The next step is layout. So there are two steps that you have to do. You place yourself and then you route into it. And then you have some special nets that you have to treat specially. You have the clock tree synthesis because that is to be connected to a lot of things. So you need to treat that differently. And also the power connections you have to treat differently. And that also has to be done by your place in a route tool, as it often calls. Then your place route tool has done. And then before you send it to the foundry, you do sign off. And this is to be sure that it will work when it comes back from the foundry because you pay a lot of money. And there are a lot of three letter words used there. You have the DRC, which is a design rule check. This is rules on the layout that the foundry gives that you have to obey. And if you don't obey them, then they will just reject your chip. Then you have layout versus schematic. During synthesis and layout, people can also transform your chip, your design. But then you have to be sure that it still does the same functionality. And then you do layout versus schematic. And also, later on, the logic equivalence check. Then also, you probably want to meet certain timing. You want to run this at 100 megahertz, so you have to check the timing of your chip, which is called static time analysis. Power, also IR drop. So a lot of things are consuming power. And it means that the resistive network of your power will cause voltage drop. And you have to be sure that the voltage doesn't go too low on your chip. And you also have the problem with scaling down that signals are coming close to each other if one signal can influence a signal next to it, so it can have crosstalk. And you have to check all these things if nothing is wrong with that. Luckily, for mature nodes, for older nodes, you need much less strict checking than for next generation nodes. So the tools become more important for the state of the art nodes. Then, after you have checked everything, you tape out to the foundry, you wait a few months, you pay, and then you get something back. And then you have to test. You can do its functional test, just run program. It's run it like it used to be and see if it works or not. But also, they also test it with ATBG, with our test patterns that they just run through the things to see if there are no shorts or opens in your circuit. And there are tools for that to do that automatically. So now let's focus on open source tool chain. First of all, I started to assembling my course. I had a TAT and a T65, which is a Z80, a MOS 6502 compatible. They were in VHDL. And then at the AOI 68000 core, and it was in Verloch. So it means I need to be able to put two different languages on the same chip. So, and I think if you want to have a vibrant open source IP portfolio, this is a general requirement for having an ASIC tool chain flow. You should not in advance eliminate IPs because you're hitting in a certain language. So I'm an old school guy, so I still use Emacs for editing. And then I use proprietary FPHU tools, also the Quartus and Ease, and now we have Vivavo of Xilinx. For simulation, I use Cocoa TB, which is a core routine test bench feature for Python that you can couple with normal simulators, the Icarus Verloch for Verloch and GHDL for VHDL. But for mixed language, I don't find anything good yet. So I do still use the model sim which is provided by the FPGA tools for that. For synthesis, you have Fiosys from the Qflow for Verloch, and I have access to the VerificParser which provides VHDL support. So there was Alliance from France for the University of Paris that was done in VHDL, but it didn't follow the new standards. And this course used the new standards of VHDL, so I cannot use that at the moment. And also Tristan told that GHDL synth beta is still mainly a proof of concept, so it didn't support a lot of features that were needed for my course. So for layout, you have Kuflo, the tools there, you have GrayWolf and QRouter, and then you have Coriolis, which is also now developed in the University of Paris, and they have three tools there. So I had my course, I had the RTL codes, I synthesized them, and I put them through the tools, and I see that there is still room for improvement, but I'm in contact with the both authors of these tools and I'm convinced that this is not a bottleneck, so they are very real nice people, and it's just because I'm using a new node, a new technology that they haven't used before that they have to do some setup, and that's not a problem. So I don't think that is still lacking for the flow. Then you have a sign-off, so the DRCLVS supports, you have a lambda, a magic, an electric, but they're quite limited. Of course I'm using all the technology nodes, so it's not the requirements or not that high. Production, I'm looking at different foundries, CSMC on CME, 0.35, 0.25 technology. So the silicon starting costs start from below 10,000 euro or dollar, and you can also have features like five-volt or higher voltages even, so it should also be perfect for analog design. But when you have very low volume, that is not the only cost, you have also other. So they have a minimum area that you need to take and then you want to sub-dise them and that will cost money and that costs more than the die itself, than the one thousandth of transistors you pay for or cheaper than just sub-dising the die. And also to start up the setup, so packaging, so to package your chip in a package, they start with a few thousandth of that setup cost. So you need to sell a lot of things to get that in a good find. So if somebody has references that want to do maybe packaging for a higher unit cost but lower setup cost, I'm all ears for that. I also investigated that, but also there so the setup cost is towards adding contact with for chip on board. They had an engineer next to the tool all the time and you pay the engineer, which is also a lot of money. But if you have references there that people want to do for low volume chip on board, I'm all ears also. So for tests, I have a TTAG interface where you can do boundary scan. So it means that you can put IOs in a certain state so you can test your PCB. For ATBG, the logic is small enough that I will just test it with programs that are running on the CPUs to see if the functionality is okay and test the memory that way. So for the PCB tool chain, I'm using KeyCut. You say it's sponsored by KeyCut also. So it has a lot of features, but sometimes I still have the feeling I'm fighting with the tool somewhat. It's not, even for an engineer, to me it's not user friendly. But maybe that's because I'm used to other programs with other ways of doing things. So maybe I haven't used it enough yet. So, you'll see. For production of the PCBs, I will go to probably to Euro circuits. There, it's a European, I think it's in England based. You can just upload your KeyCut file there and they will give you a quote. And they even have now providing assembly services and I, so they can do them. Test, so for testing, I am planning to do eating my own food. So I'm planning to use an FBA job board with a little microcontroller to test actually the boards that I will make. So to come to the summary, is an ASIC made with fully open source tool chain possible? Yes, I think it's possible for the mature technologies, certainly. But I think we should try to get some renewed effort in mixed language support for the tools. For smaller nodes, new tools are needed for sign-off and test, but also that the setup cost will become higher. So probably the older nodes are good enough and you can do a lot of things with them. Is it affordable? I think it should be affordable for crowdfunding, low volume products. And if you have reference to reduce the setup cost more, I'm all ears. Any questions? So it's question, how I have access to TSMC and Onsemi. As I said, I work for IMEK, and IMEK is a VCA for TSMC. So they do provide services for IMEK. So on that side, it's also easy because I'm working there so I can talk with the guys there, so yeah. So he's asking if you're using PDK of university. No, I'm using the PDK of TSMC itself and a standard cell library. No, no. So you only need the liberty files and the left files to be able to do synthesis and play that out. And these are available. Yeah, and these tools, the Qflow has support for the def and the left files and the dot liberty files. You just can read the liberty file for time information and the players can read the def, the left file of the standard cell library. So he's asking if I'm using the Moses libraries. No, I'm not using because the Moses are based on lambda and I prefer real the real dimensions. I'm just using a PDK that you can access from TSMC and a standard cell library. Yes, you can download them if you haven't signed an NDA. And before signing an NDA, you have to give the impression that you will order something. So, yeah. So he's the question about the legal part. It's mainly about these NDAs. If you sign them, what does it impact me? You don't know. And actually, in order to sign an NDA for TSMC, you have to have a company. So they don't want you to sign in person. And it had to be, so in Belgium, you can work as an independent alone. And that was not enough yet. You really have an incorporated company to sign the NDA. And that's why I have now a company. So I want to have that in intermediates that I take care of these stuff and that you can just design. Of course, I cannot give you the standard cells, but I'm working on that to solve that. Maybe that's how we'll do in the cloud, that you just test your codes in FPGA. And then, there is a Jenkins type of thing that just runs through the synthesis and then you get the results back, but you don't need the files to download the files to be able to do it. That's still open for discussion. He's asking if there are standard cell libraries and if they work with these existing foundries. I think one open source GPL standard cell library, if you go to vlsitechnology.org, there you can find these standard cell libraries, but they are GPL licensed. So it means that the code, all the RTL code also has to be GPL licensed. You cannot use it for a non-GPL licensed code. And I want to have something more usable that the standard cell library doesn't decide which license you have to put on your RTL code. Actually, he's asking if I've seen the guy who's making chips in his garage. I think I saw a video about that, but I want to stay away from chemistry, so I don't want to do that. That's too dangerous for me if I start doing chemistry. And anyway, yeah. There is some 3D printer. Yeah, and about 3D deep-pinking. You have now, I think, inks that you can use for 3D deep-pinking where you can make some kind of schematic type of things, but that's maybe then how to make a transistor with that and having hundreds of transistors on a sheet of paper, that's another question, huh? Yeah, yeah, okay. Which, where was it? Yeah, but which university or in China? I guess it was Hong Kong. Ah, Hong Kong. So he asked if I'm aware about facility of point 18, point 13, where they provided. I was not aware of that. I know that in Japan is also happening something like that. I met a guy at the University of Paris there, but there the language barrier was a problem. Everything was in Japanese, so. But if you can keep me in contact, I'm sure. So I'm still open for new. I haven't started it. With the land, living in China. Yeah, so it's for Switzerland, but living in China. Okay, yeah. Okay. Thanks.