 Hello, and welcome to this presentation of the STM32L4 flash memory. All STM32L4 flash features will be presented. Please note that this presentation has been written for STM32L47X48X devices. Key differences with other devices are indicated at the end of the presentation unless otherwise specified. The STM32L4 embeds up to one megabyte of dual bank flash memory. The flash memory interface manages all memory access, read, programming, and erasing, as well as memory protection and option bytes. Applications using this flash interface benefit from its high performance together with low power access. It supports read while write, has a small erase granularity, a short programming time, and allows dual bank booting. The STM32L4's flash memory has several key features. It has up to one megabyte of dual bank flash memory with a read while write capability that can program or erase one bank while executing code from the other bank. The erase granularity corresponding to the page size is only two kilobytes. A page, bank, or mass erase operation requires only 22 milliseconds, and the programming time is only 82 microseconds for a double word. The adaptive real-time memory accelerator with an instruction cache, a data cache, and a prefetch buffer allows a linear performance in relation to frequency. The flash memory supports error code correction, or ECC, which is 8 bits long for each 64-bit double word. A single error is detected and corrected. A double error is detected but not corrected. The flash memory is divided into two banks, each having a main memory block containing 256 pages of two kilobytes each. Each page is made of eight rows of 256 bytes. Each main memory block has an information block which contains three parts. The first part is the system memory which is reserved for use by ST Microelectronics and contains the bootloader. When selected, the device boots in system memory to execute the bootloader. The second part is a one kilobyte one-time programmable area. This area is located in bank one only. The OTP area cannot be erased and can be written to only once. If one bit is at zero, the entire double word can no longer be written, even with the value zero. The last part contains the option bytes for configuring user options. This slide shows the flash memory map. There are 256 pages in bank one starting from page zero and 256 pages in bank two starting from page 256. The page number MSB corresponds to the bank number. The page number is used in the software procedure to erase a page. The flash is dual bank memory with read while write and dual bank boot capability able to boot from either bank one or bank two. The BFB2 option in the user option bytes is used to select the dual bank boot mode. When the BFB2 option is set, the device boots in either bank one or bank two depending on the valid bank. When the BFB2 option is cleared, the device always boots from bank one. The dual bank option is used to select either a single bank or a dual bank for the 256 kilobyte and 512 kilobyte device part numbers. For instance, when dual bank is selected for 512 kilobyte devices, 128 pages are in bank one and 128 pages are in bank two. The first page name in bank two is always page 256 regardless of the device's memory size as the page name MSB refers to the bank number. With a dual bank memory, it is possible to read from one bank while programming or erasing the other bank. Code execution is not stopped when the flash memory is being programmed. When programming or erasing data in the same bank, the AHB is stalled as long as the flash memory controller is busy. Using the FB mode bid in the system configuration memory remap register, the two flash bank addresses can be swapped. When this bid is cleared, bank one is mapped at address 0x0800000 and aliased at address 0. When this bid is set, bank two is mapped at address 0x0800000 and aliased at address 0 which allows the device to boot into bank two. The dual bank boot allows a safe firmware upgrade as the previous firmware version is still present in the other memory bank. The dual bank boot is managed by the bootloader. The device boots in bank two using the BFB2 option bit programmed in the flash option bytes. The boot pin and boot option are configured for booting in flash memory. If the BFB2 option bit is cleared, the device boots in flash bank one. If the BFB2 option bit is set, the device boots in the system flash memory. The bootloader checks the bank's first address as it must read there the stack pointer at that location. If bank two's first address is a valid SRAM address, the bootloader swaps the banks to remap bank two at address 0 and jumps into bank two. If it is not valid, the bootloader swaps the banks to remap bank one at address 0 and jumps into bank one. Note that the bootloader uses resources in SRAM 1 from address 0x2000000 to address 0x20001000 so this SRAM area must not be used by the application when the BFB2 option bit is set. The flash memory embeds an error code correction function to ensure robust memory integrity and safety. The ECC is 8 bits long for a 64 bit word. In the case of a single error, it is corrected. The ECCC bit is set in the flash ECCC register and an interrupt is generated if it is enabled. In the case of a double error, it is detected but not corrected. The ECCD bit is set in the flash ECCC register and a non-maskable interrupt is generated. When an ECCC error is detected, the failure address and associated bank are saved in the flash ECCC register. The programming granularity is 64 bits, in fact it is 72 bits with the 8-bit ECCC. There are two programming modes, standard mode for the main memory and OTP and fast mode for the main memory only. In standard mode, the flash memory checks that the double word is erased before launching the programming. In fast mode, 32 double words are programmed without verifying the flash location. The flash programming time is only 82 microseconds for 64-bit double words. To program one page, 2 kilobytes, 20.9 milliseconds are needed in standard mode and 15.3 milliseconds in fast mode. For the complete bank, it requires 3.9 seconds in fast mode. The page erase time is 22 milliseconds. It also requires only 22 milliseconds to erase one or both banks, as both banks can be erased simultaneously. The short programming and erase time, plus the small page size, make it convenient for data EEPROM emulation. A fast programming mode allows you to program 32 double words faster than in standard programming mode. Only the main memory can be programmed in fast programming mode. The flash address location contents are not verified by hardware before programming in fast mode. The 32 double words must be written successively. The high voltage is kept on the flash memory for all programming. The maximum time between two double word write requests is the programming time, which is approximately 20 microseconds. Consequently, interrupt should be disabled to ensure that the 20 microseconds between the two word write requests is not overpassed. The minimum clock frequency must be at least 8 megahertz in fast programming mode. This slide compares standard and fast programming modes. Standard mode can be used to program the main memory and OTP areas, while fast mode cannot be used for OTP programming. Standard mode allows programming 64-bit double words or 8 bytes, whereas fast mode only allows programming 32-bit double words or only 256 bytes. In fast mode, the address location content is not checked before programming. The CPU clock frequency must be greater than 8 megahertz and interrupts are prohibited. It takes 2.6 milliseconds to program 256 bytes in standard mode and 1.9 milliseconds in fast mode. The flash memory is guaranteed for a minimum of 10,000 cycles up to 105 degrees Celsius. Data retention is 30 years after 10,000 cycles at 55 degrees Celsius, 15 years after 10,000 cycles at 85 degrees Celsius, and 10 years after 10,000 cycles at 105 degrees Celsius.