 We will now go to a specific hardware description language called VHDL, which is a very popular hardware description language. So, having understood the general principles of hardware description language, we now want to pick up one specific hardware description language and this hardware description language is VHDL. You would have, I am sure you would have heard of this language. For programming concept, it is structured like a programming language called EDA. This is a very formal language and in fact, VHDL is equally a very formal language. This is to be contrasted with very long parts of which we will do tomorrow, which is constructed like C and is not half as formal as VHDL is. Now, if you recall, we had seen that hardware description languages are used for VLSI design and therefore, various uses of a language are for describing the hardware, for modeling hardware, for simulating hardware, for early performance estimation of system architecture. That means, whether at all I have any hope of meeting my specifications or not. For synthesis of hardware, if possible, my work should be done by a program. If the specifications are given in a particular way, then what hardware will meet this specification should be automatically generated. That is called synthesis and finally, for fault simulation. This is say at the time of testing, if my hardware is faulty, then what kind of things shall I see at the output and then to make a dictionary, so that if I see those kinds of things at the output, then I should come to the conclusion that such and such fault occurs inside my actual hardware. So, all these things are done using an actual hardware description language and facilities for these are provided in this language. Now, the basic design element in VHDL is called an entity. The entity could be your entire circuit, it could be the components of this circuit or it could even be the circuit with your test instruments in the process of testing it out. Therefore, any hardware object of whatever complexity has to be made first into an entity. The entity represents a template for this hardware block. It does not describe what this hardware block is made up of and how does it operate. It only gives you essentially a pin diagram of a component of this type. So, it describes just the outside view of a hardware module, namely its interface with other modules in terms of input and output signals. The actual operation of the entity is then described by a different module called the architecture and the architecture lies under the entity. Architecture is always for an entity and architecture cannot be standalone, whereas entity can be standalone. Here is an example. By the way, VHDL has changed substantially over the years in response to various demand and therefore, there are various variants of VHDL. When I give an example, I will often specify what kind of VHDL is it. This refers to the year in which these things were introduced. So, the VHDL 87 was introduced in 1987, VHDL 93 6 years later. So, certain things have changed with time in these languages. So, this is how a typical entity would be specified. Entity in bold letters here, I have letters which must occur as they are. The rest will be supplied by you for that specific entity. So, entity and here you will give the name of the entity. It could be for example, a D flip flop or adder. So, you will say entity adder is, notice that the word is must occur as it is. It is in bold. So, entity adder or whatever name is and then two lists optionally follow this. One is a list of generics. The other is a port list. Generics are like hash defines in C. These are values which can be assigned late. That means these are constants, but these constants can be assigned based on some choice. So, those are called the generics. For example, you might have described an AND gate, but the delay associated with this AND gate could be described as a generic. Then this same AND gate description can be used at different places and to give a specific value of delay, you can declare it as a generic. So, it is just like a hash defined in a C program. These are essentially constants, but which can be defined at runtime. So, those are there in this list. This list is optional and very often might be absent. The second list is that of ports which says what input and output signals are connected to this entity. And finally, we give the keyword AND entity name. In the previous version, the word the AND entity name was simply AND name and this rule was somewhat unpredictable. For entity, the keyword entity did not occur. For architecture or component, it might be required. So, this whole thing has been made very uniform in the new version of VHDL which is VHDL 93. This something is architecture something is and then AND entity that name AND architecture that name. However, most actual languages support both variants. So, they have to be backward compatible and a modern VHDL program might accept this kind of description as well as this kind of description. Here is an example of an entity. Entity flip flop is so the name is flip flop. So, entity flip flop is generic T-prop delay length. That means I am going to declare a generic called T-prop propagation delay and its type is of a type delay length which I would have declared earlier which is of type time. And port signals called clock and D are inputs and are of type bit. A signal called Q will be my output and will be of type bit. So, essentially all signals connected to the flip flop are described in this port list. Any generic that I may require for simulating its behavior will be declared in this generic list and this is in fact optional. And then AND entity flip flop notice that in VHDL 87 I would have just said AND flip flop. So, the entity declares port signals their directions whether it is input and output and data type. Now, this only gives you an outside view of this entity. What makes it tick? What makes it work? That is done by an architecture. So, the architecture describes how an entity operates and an architecture must always be associated with an entity. So, you must say whose architecture it is? Is it the architecture of a flip flop? Is it the architecture of an adder? Is it the architecture of a counter? So, therefore, the architecture is always with reference to some entity. Now, for a given entity there can be multiple architectures. For example, I may have an entity called an adder and I may have a ripple carry kind of implementation for it. So, that is one architecture. So, I have an entity called adder, but the architecture is called ripple carry. For the same entity adder, I can have another architecture called a carry select adder. So, now an entity can have multiple architectures. Each architecture is a different way of implementing this architecture of this entity. Now, the architecture can describe the working of this in one of two ways. It could describe it in a structural style. It could say that this the architecture of the D flip flop contains two NOR gates cross connected. So, it is describing the D flip flop as a list of components and their interconnections or it might describe it behaviorally. That means, it might say that when the clock has a positive transaction, the output Q should become the same as D. So, the architecture could be structural. It could describe components and interconnects. It could be behavioral or indeed it could be mixed. Parts could be behavioral and parts could be structural. Now, here is the syntax for an architecture. You say architecture and this is the name of the architecture. So, you say architecture name of entity name is. Then you declare your various signals and variables. Then the keyword begin. This is followed by various concurrent statements or concurrent blocks. Remember, a concurrent block can then have sequential states. Then end architecture name. Notice that in case of VHDL 87, the word architecture was required in case of an architecture, but was not required for an entity. VHDL 93 has made it uniform. Everything requires what is ending and what is its name. So, architecture for example, I could have two architecture for an adder. I could have architecture ripple carry of adder is and then declare all the signals carry in, carry out, a, b, sum, etcetera begin. This would then be followed by concurrent statements and finally, end ripple carry and architecture ripple carry. Similarly, I could have another architecture of the same adder and then it will be architecture carry select of adder is. Declarations as before begin all the logic for implementing a carry select adder and finally, end architecture carry select. So, now we have one entity called adder and two architectures for it. This is another example of architecture. In this case, I am describing a deep flip flop. So, fair enough now we understand entities and architectures, but this architecture in case of structural description will require components which are interconnected. Now, these components need not all be basic components. It might be components for example, I gave you the example of an AT-AT5 when I said that ALU will be a component. Now, ALU will be another VHDL entity and I must now make it into a component so that it can be instantiated in the AT-AT5 entity. So, an entity architecture pair actually describe the component type. For example, a deep flip flop described by an entity and architecture describes how deep flip flops in general operate. That means what are the input signals to any old deep flip flop, what are the pin diagrams of any old deep flip flop and what is the behavior of any old deep flip flop. But for a specific deep flip flop, you must first make it into a component and then instantiate that component. So, this is like saying these are the properties of human beings and then you instantiate a human being and say this is Dinesh Sharma, who is of type human being. So, Dinesh Sharma is then a component, indeed you can have a component type as well, we will come to that later whereas Dinesh Sharma is the entity architecture pair, human being is an entity architecture. So, each instance then needs to be differentiated by a unique name. For example, in a circuit you might have four NAND gates, now the entity architecture is for a NAND, but these four NAND gates are different, their inputs are different, their sensitivities are different therefore, each should have a different name. So, when you instantiate a component then each must be given a unique name. So, therefore, a particular instance of a component which should have a unique instance name and that name is associated with a component type and that component type is then associated with an entity architecture pair. So, this is the hierarchy in case of VHDL, when you place a particular component for example, here is an example that you have placed a particular instance called U1, which is of the component type D flip flop and to find out what D flip flops do, I will go and look up the entity DFF using the architecture LS7474. So, therefore, there is a sequence of mapping, a particular instance of hardware has a name, this name is associated with a component type, the component type is then associated with an entity architecture pair. This is the association in case of VHDL, modern versions of VHDL allow you to map a component instance directly to an entity architecture pair, but this was not available in VHDL 87. So, if you want your description to work with all versions of VHDL, then you might want to do this detailed mapping. Now, this tutorial which I am showing you has also been uploaded to Moodle and it has 133 foils, obviously we are not going to have time for all of these. So, I am going to skip many of these again and essentially show you something which is relevant to the lab that you are doing. However, please go through particularly these data types and so on are very important because you must learn to distinguish between data type and object type in VHDL otherwise you will get confused. Unfortunately, we do not have time for all of these types right now. Let us now go to see how I describe structurally because this is what you are going to do. So, structural trial describes the design in terms of components and their interconnection. Each component declares its ports and the type and direction of signals that it expects through those ports. For example, here is a circuit which is described structurally that means we see various components and their interconnection. How do we put it down in VHDL? So, notice that I have u 1 here, it has p 5 and p 6 as inputs, p 1 through p 4 as output, p 1 and p 2 of u 1 go and connect to p 2 and p 3 of u 2 whereas, p 3 and p 4 go and connect to p 3 and p 4 of u 3. One output of u 3, p 5 comes back and connects to p 1 of u 2 whereas, p 6 as of u 3 and p 6 of u 2 form the output. So, this is what we want to describe. In order to describe this, we must describe internal signals, these signals namely s 1, s 2, s 3, s 4, s 5, s 6, etcetera reside and s 7 here. They reside only inside this hardware, they are not visible from input or from output. That means, there is no outside view of these signals. These are like PC board tracks, they occur inside the PC board and outside you do not see those signals at all, those signals are not visible. So, these signals must be declared internally and the corresponding ports must be mapped to those signals. So, for example, here p 1 is mapped to s 1, p 2 is mapped to s 2 and when different ports are mapped to the same signal, then they are supposed to be interconnected. For example, s 1 is mapped to p 1 here whereas, s 1 is mapped to p 2 of u 2. What it really means is that p 1 of u 1 and p 2 of u 2 are connected. So, when the same signal appears in one port of one block and another port of another block that means, this port of this block and this port of this block are connected together. So, this clearly means that we need to map specific ports to specific signals. So, a structural article architecture which is purely structural will consist of component declaration to associate component types with their port list, signal declaration like s 1 through s 7 that we just saw. Component instantiation, this was just a declaration. Here, we place the components and then configurations which will do the binding that we had talked about. That means, to bind component type to entity architecture pair and very often it is tedious to do it one per one. There may be lots of similar components. For example, in an 8 bit register I may have 8 D flip flop or in a memory I may have thousands of flip flop. So, therefore, to do it one by one will be very tedious and therefore, we have repetition grammar which allows you to place components of the same type, but in large numbers. So, this is what structural architecture contains. A component declaration is very similar to an entity declaration. In fact, the syntax is identical except that rather than using entity you declare a component. Since, our time is a little short that is all we will do it is quite easy to see it is in fact identical. Now, how do you place a component? Suppose, you want to place a D flip flop. If you are directly placing an entity which is possible in VHDL 93 onwards, then it is very easy. You give the instance name for example, suppose you had 4 flip flop. So, you will give this name as u 1 or f f 1 colon followed by the keyword entity. Then the name of the entity for example, D f f and within brackets the name of the architecture. And then generic map the value that you want to give to the generic variables of this entity. And port map which will give a signal list and these are the signals which will be mapped to the corresponding ports of this entity. So, this port map will look very much like the port declaration of this entity, but this will contain signals, this will contain ports and the corresponding signals will be connected to the corresponding ports. This direct instantiation is not allowed by VHDL 87. We will just keep the HDL 87 case and go to an actual example. Here is an XOR gate which is constructed of 4 NANDs which are connected like this. Now, we always these components known components reside in a library and the default library is called the work library. So, as we describe components they keep on being added to a database called the work library. So, we begin with the NAND say entity NAND 2 is and this is an entity not a component and it we do not use any generics here and we say it has 2 ports in 1 and in 2 which are input of type bit and it has an output P which is of type output and that is also a bit and entity NAND 2. And then we declare a very trivial architecture of NAND 2. So, trivial is the name of this architecture not an adjective. We say architectural trivial of NAND 2 and architecture is always of an entity. So, of this entity. So, architecture trivial of NAND 2 is assigned to P this compound symbol means assigned. Assigned to P the value of not of in 1 and in 2 and is a built in function. So, I am saying take the NAND of in 1 and in 2 not that value and assign this to P that is the architecture of the NAND. So, now that NAND has gone into my work library. So, I say use work dot all that means use everything that you find in the work library. And then say entity XOR is port A and B these 2 ports. By the way BHDL is case insensitive capital AB are the same as lower case AB. So, port AB are in and type bit and AXB is an output port and is also of the type bit and this ends the entity. The architecture is described by placing all these components. So, we will say component declaration that NAND 2 input with the same kind of thing and for all NAND 2 in that means all instances which use component type NAND 2 input use the entity NAND 2 with the architecture trivial. Now, I declare notice an architecture begins with declaration. So, these are only the declaration and then signal S 1, S 2 and S 3 which are of type bits. So, these are just declarations like your declarations at the beginning of the C program. Then begin and now I start placing components. N 1 is this component. I use the word component because I am placing components not directly entity. The name of the component is NAND 2 input and I port map its values to AB and S 1 here. So, AB and S 1 the order is 2 inputs and the output. Now, I place this component N 2 component of the type NAND 2 input and then port map inputs to A and 2 S 1, A and 2 S 1 and the output 2 S 2. I place component N 3 instance N 3. So, I say N 3 is an instance of a component. The name of the component type is NAND 2 input and I port map this particular instance to B and 2 S 1 and the output 2 S 3. And finally, I place N 4 which is an instance of the component type NAND 2 input and I port map its inputs to S 2 and to S 3 and the output to A X B and this ends its architecture. So, this is the way that we describe hardware in VHDL. I think we are through our time here. We will stop here, but this is a very long lecture. As you can see this is the 43rd slide of 133 slide. So, there is a lot of information here and if you are interested in VHDL, then you can go through this and it will help. There are also lots of books and one particular book is available for free, but this is very outdated. So, that outdated book you can have for free, but other there are excellent books available on VHDL if you want to learn it from scratch. However, basic electronics this should do and using this now you can place various kinds of gates and now when you compile it for your CPLD board, then it will make the appropriate it will choose the appropriate logic blocks and make the appropriate connection to place a circuit in this. A demo has already been given to you for the CPLD block. We will take a stop here for this lecture. Good afternoon sir. My first question is what is the basic difference between very long and VHDL languages and which one is to be preferred in academics and which one is used in industry and why so? Over to you. The difference is in style. As I said VHDL is a very formal language. Everything has to be clearly declared and then mapped and there is a very deep hierarchy. As we saw for example, you have entities which have an architecture and entity architecture is then mapped to a component type. That component type is then mapped to an instance and then you have one single gate on your board. So, it is in that sense a very formal and correct language. However, because of that it is not ambiguous. The style, the programming style is like a language EDA which is not widely known. So, therefore, in that sense VHDL is slightly difficult. Very long on the other hand is a very informal language. It is based on C which is quite familiar to most people and therefore, it is a convenient language to use. On the other hand, it is a somewhat ad hoc language and can be quite, it can be, you know it can do surprising things. So, it can be ineffective in a place where you want 100 percent reliability. So, these are the properties of the language. There is nothing better or worse about either language. In my design, I use both of them equally. In general, modern industry prefers very long because then it finds easy to hire people who are familiar with C and they learn very long, very quickly and the productivity can be somewhat better. On the other hand, those people who are, who put much more value on correctness and reliability, for example, defense space and such agencies, they have a natural preference for VHDL. However, both languages are widely used in academia as well as in industry. You pick whatever is natural to you in which you can get manpower and what you can easily use. In fact, in academia, we teach courses which include VHDL as well as very long. So, there is nothing to recommend one language over the other. If you have specific requirement, then you choose the one which meets your requirements. If you do not choose according to convenience, there is nothing better or worse about the tool. My next question is, how do we recognize different types of feedback networks looking at a circuit diagram? Ideally, this question should be taken by Professor Joseph Jones. So, you should ask him when he comes up next, but I will give you a quick answer. When you look at a circuit diagram, look at the circuit, look at the connection from the output back to the input and find out what is the combined input. How do you combine the input signal with the output to feed an input? If that input is a voltage, then it is voltage feedback, otherwise it is current. Also, if the feedback circuit is in parallel with the input circuit, it is parallel feedback. If it is in series with the input circuit, then it is series feedback. So, this is a generic rule, but in fact, it is best illustrated by examples. It is very difficult to follow. It looks very easy to say here, but it can be quite confusing in actual circuits and therefore, you may have to learn it with actual circuits. I suggest that you place this question with Professor Joseph Jones, who has been doing this circuit. Excuse me, sir. Just want to know about how we will be describing the arrays in VHDL. Like I want to design some 2-D array. I should use some packages by initiating some libraries and packages. Can you explain with an example? Yes, arrays are essentially declared. VHDL is more powerful than verilog in this way. Verilog naturally permits only one dimension and with a special construct quasi 2-dimensional, but more than that, it is very difficult. Whereas in VHDL, you can declare variables or arrays with multiple dimensions and you have to declare a variable type by saying type this is and then the base type and what discrete values the indices of various types will take. If you go through my notes, the early part where I had said that the variable types are declared here, you will find information based on that, but otherwise it is like any programming language. You have the type of every member of this array and a type for every index of this array. The index has a type. It is not always integer. It can be any discrete type. Any variable which takes discrete non-continuous values could be an index and the value returned is a value. For example, you could have a bit or any kind of variable. So, for example, you could declare a byte to be an array of 8 bits and you could declare a register to be 2 bytes. So, however, the exact syntax is very difficult to take in a very short time here. However, the lectures that I have uploaded to Moodle, they describe this in detail and you should look that up and most textbooks also do a good job of describing. Sir, in one of your lectures, you said that in 741 operation amplifier, the band width is, we cannot use it beyond 10 kilohertz, but in literature, we say that the band width is infinite and for practical purpose, it is huge. Is this huge band width for 741, I see it is just 10 kilohertz. So, could you please elaborate upon this? One more question. When we are implementing the oscillators with the help of transistors on breadboards, we face difficulty, but when we are using the same RC phase shift to oscillate with the help of operation amplifier, we can realize it very quickly. So, what is the reason? Please throw some light on it. What are you, sir? I will take your question sequentially. The infinite band width refers to an ideal op-amp. 741 in matters of band width is very far from being an ideal op-amp. It is pretty good in terms of gain. It has about 60 to 80 dB of gain. That means, its voltage amplification is between 1 to 10,000. So, it is a pretty good. In fact, it is close to 10, might even be over 10,000 in most chips that you buy. So, its gain is pretty close to what could be considered infinite. Its input impedance is pretty high and output impedance is pretty low. So, in those respects, it is close to an ideal op-amp. Unfortunately, its structure is such that this gain does not remain at high frequency. So, it is far from being an ideal op-amp. So, when we analyze an op-amp, at that time we have to make these approximations that it has these nice properties. But real op-amps fall well short of those properties and 741 falls short particularly in the area of band width. In fact, the flat band width is even below 1 kilohertz. The usable band width at which gain is high enough though it has started dropping is of the order of 10 kilohertz. So, it is not a good high frequency amplifier. In fact, op-amps in general have band width limitation because it is very difficult to have very high frequency and very high gain at the same time. So, this high frequency and high gain occurs only for ideal op-amp. By the way, for students a very often immature error made by them is that they assume that an op-amp will work at any frequency and when they want to amplify let us say something like 100s of megahertz they just put an op-amp which will never ever work. So, you must understand that only for applications in those frequency ranges that an op-amp will behave like an ideal op-amp at high frequency it will not. Your second question was about breadboard and PC board implementation of oscillators using ICs and op-amps and transistors. Actually, if the required conditions are met even on a breadboard it is quite easy to make an RC oscillator it is not difficult. However, notice that a single transistor amplifier the bias can be upset by R and C that you put and if you are not careful then you might end up changing the bias on the transistor amplifier and you require a minimum gain of around 30 to compensate for the attenuation in the RC circuit. By the way I have put up nodes on your model side which describe the quantitative detail in full detail for an RC oscillator. So, if you look at that algebra you will see that the attenuation in the RC network is of the order of 30. Therefore, a minimum gain of 30 is required from the circuit. If your single transistor amplifier is not very well designed and has gain less than 30 in that case it will not oscillate. Whereas, op-amps have an open loop gain of tens of thousands therefore, getting a gain of 30 is not very difficult. It is for this reason that you find that that oscillators can be quickly constructed on a breadboard using op-amp whereas, it is quite a tricky job to do it do the same thing. But the question is not in breadboard, but it is in the use of the amplifier. You need an amplifier with sufficient gain and if you have a good quality breadboard such that resistances are not compared comparable to the RC that you are using in your circuit. You should be able to get an oscillator going on a breadboard using a single transistor amplifier as well. We will bring the interaction section to a close at this point.