 In this lecture, we are going to see some more protocols, this is between different from the very price, this is for interconnecting different models with a controller on the onsite ok. So, you will see in any embedded system an I square C and spy protocol be used there at a bus. So, let us have a brief introduction about this and then of course, this is universal synchronous asynchronous receiver transmitter, this is a serial controller serial code controller then and then we will see the general purpose IO as the to complete our discussion on peripherals ok. This we have covered a few portions of peripherals we saw in the last lecture and then this is the continuation of that and with this we will be completing the both the categories of peripherals and interfaces that that will be used in an ARM SOC ok. It will be used for any any any other source to we have particular about what is being used in the process of the ARM SOC ok. So, what is I square C? It is a integrated circuit bus. So, you can see that it is using two ICs between two ICs when you it is not like a bus within the SOC ok. Then it is it is AHB is an example where different modules in the SOC get connected to the bus as the name implies inter integrated that is between two ICs physically there are two ICs in the system and then it is connected through an I square C bus ok. So, there will be some things here there will be some things here and then they they are connected through an I square C. So, there are physical cables a number of lines in the cable and then what is the kind of protocol that needs to be run on both the side of the ICs ok. What kind of signals need to be sent over this line? What is the amplitude and what is the frequency ok and then what is the format? Now, if it is a packet what is the data format where is the how suppose an I square C bus could be used to connect multiple ICs. So, we may have to address one of the ICs in the bus. So, that one of them is called as this kind of various things come similar to may be you know in the particular network scenarios where we have LAN cables and then some system coming and then we have no other computers in another network. So, these connect multiple computers and switches using these multiple computers are connected to an IC. So, what we are seeing is a I square C is a multiple ICs in a PCB or may be multiple PCB you know with the very short distances they are connected multiple ICs in a PCB or multiple PCB they are connected and they also form a kind of you know multiple devices can be there on the strip on the bus and then they communicate with each other. So, it is like since these two address of the thing you know one can transmit and other can receive and similarly the other and other device can transmit the other you know two end points are there. So, you know E 1 end point E 1 and E 2 E 1 can you know transmit something in which E 2 will accept and E 2 will transmit and E 1 will accept. So, this is the kind of communication that we are going to talk when we talk about I square C this is what we mean. So, an inter IT bus is often used to communicate across circuit boards it is a simple low bandwidth short distance protocol. It provides good support for communication with various low on board peripheral devices that are accessed intermittently. So, the I square C bus is not kind of a like an inter IT bus where the communication happens continuously. This is very very you know slow devices. So, once in a while they communicate. So, this is meant for a low bandwidth low the data rate is low as well as the frequency of communication is low as well as the amount of data communication communicated over this bus is also less. Most available I square C devices are made at peak of 400 kms. So, this is not lower than the mdts and dbps bandwidth that they see in the bus. So, some venturing up will be low megahertz may be maximum is megahertz. So, I square C is a easy to use to link multiple devices together since it have built in addressing scheme ok. So, that device coming up ok it is like multiple computers are connected to LAN network. So, each computer with a network card in it or network port in it it will have its own MAC address as you all have to know if you connect MAC address it will need to a particular device which is in the LAN network or you can make ok. So, similar to the any device connected to I square C bus they have their own unique ID ok. That means, you can differentiate it is like a pattern way. So, any device can be connected to I square C and then they can still be there with those clashing with the addresses of other devices. See that is very important when we want multiple devices to co-resist in the bus because we want to uniquely address them. Any device wants to communicate with any other device in the network they need to have unique address on the network otherwise they will not be able to communicate correct. So, in I square C bus what happens is the devices will have its own unique built-in addressing scheme. So, if they will have their own addresses which can be used to differentiate between multiple devices in the bus. So, these are all multiple devices peripheral devices this is kind of a central microcontroller in our case it is on. So, there are only two line SBA and SBA let us see what it might be. It is a two wire serial bus it is a serial bus what is serial bus ok. So, when you have a data bus of new 8 bit wide bus B 0 to B 7 data goes. So, this is a parallel bus because all the particular talk the data on different buses with different lines physical lines constitute one data bus correct there is a parallel configuration parallel bus. So, whereas, in serial bus the data is flowed in terms of time one bit attack type. So, it goes in a sequence. So, you may consider you know you may say that at the physical level a 0 volt sorry 0 volt here and then maybe you know 5 volt here constitutes the 0 level and 1 or it could be that it is like this. So, it is plus 5 volts and minus 5 volts or minus 3 volts or whatever ok or minus 4 volts plus 12 volts. So, this kind of a voltage levels may be there, but it is in peak peak you know it is a serial device that means, what one bit at a time is then over time. So, if you want to send a 8 bit data you have to have 8 clock cycles ok. If I consider this one bit transfer rate as you know may be a tau it takes tau seconds per mille you know per date then it will take 8 tau for sending one that will be byte of data over the bus because it is sent over a serial bus ok. So, this is the kind of serial bus there are no multiple lines coming the data goes like this one after the other and the first one may be MSB or LSB based on the protocol it has to be interpreted according to the protocol. So, the two isochistic signals are serial data and serial clock. So, you can make out from the name itself one is the data bits are going and the other one is a two states when we have a data in a serial bus the problem is suppose you have a data like this this is 8 bit data, but this is the value. Now, what happens the serial bus will look like may be if I say minus is the minus 2 volts is this and then this this will change at all in the data for 4 clocks 4 clock cycles and then another 4 it remains as 1. Now, unless there is some sense of timing whether this is divided into 4 bits or it is divided into 8 bits the receiver will not be able to complain whether it is consecutive 4 zeros have come or consecutive 2 zeros have come because if it is dark late only this time may be 2 0. So, there should be a sense of clock clock needs to be there to stay whether how many bits there are to be you know what is the width of a particular transmission of a bit on the bus ok in terms of time. Then if it is longer for 4 you know suppose tau is a time then you know 4 into tau 4 of period it has been 0. So, it will be considered as 3 4 zeros have come and then 4 once have come. So, once complete data it has to be interrupted this way unless there is a sense of time it is impossible to find out what is going on the bus. So, somebody who is sampling the serial 4 the particular line the receiver needs to know what is the clock. So, that is why its clock is connected and data is also coming. So, data will be interpreted between the clock duration the middle portion number is a value where is 0 or 1 according to the level sampled may be it will sample not only 1 if 2 samples will take and then have a doubt and find out what is the value because due to noise fluctuation there may be some distance it needs to be taken care of and then finally, it decides that ok where it has 0 0 or 1. So, that is how the serial data is sampled and then dv. So, this is a suppose serial transmission of 8 bits by 8 bits of data are 7 bit device address can control. So, now since I told that multiple devices are connected and they each device has its own address assuming that there are 7 bit addresses ok then you can know that how many 128 devices can be and a 7 bit address is there we need address to each of them. In this case any data sent needs to be may be attended with a particular address. So, which is meant for which device and then the data comes calls because it is a serial device may be if it has to be time ok if I am drawing like this you know time 0 is here. So, first address comes and then may be data or I may have to draw it in a different way. So, in time wise this first address is given and then may be it depends on the protocol what is being followed normally a header will come first and then that it happens in any protocol and then control base know what to do with that particular data there anything has to be done along with the particular data there some more know information like start because of the two time protocol. So, the device that initiate the transaction on I said this is term that the master. So, please remember the communication can be this way or it could be this way. So, whoever is initiating the transfer that is for the master. So, they can communicate with each other right under us. So, the protocol should support that the master normally controls the clock signal. So, since master is generating the signal ok the sender has to control the clock signal because that sender only knows what is the data and how much of a broadway it is sending. So, it has to inform the play device also and then the clock rate will be clock also will be generated by the master and then master sends the data also. So, both should be in know should be synchronous. So, that the slave device whichever is receiving the data can amplify it according to the clock and whatever is the data at that moment 0 or 1 it will be interpreted ok. So, today is being addressed by the master it is part of this point. So, always the communicator there is a get start by master ok. If it is started by master then the value will be 1 or 0. So, if it is played and then know know it is like a read and write by master ok. Whether see it is always started by master and then says that whether it has to be a written or read. So, if it is reading that means the slave also send the data the master will read it ok. Otherwise master is writing then it is sending the data. So, this will be initiated by the master, but it will say that which slave device it is communicating with and then who is supposed to write. So, it could be a read access or a write address. The know the master is trying to access the slave either to write into it or read it only. So, it will be starting with this particular address which device it is trying to interact with and then whether it is a read or an a write. So, this will be and this is MSP. So, it is with the time MSP comes first ok with the time this data goes in the serial bus. So, whether this goes it goes in the SDA whatever serial data ok. So, SCL is a clock which is separately running know which is instance has with the particular bit must be with which the data is going and then this data may be sending sent by either a slave device or a master device depends on the data write was the form. But during the data transmission an act bit also sent by the receiver ok for every data ok. And then finally a stop is sent by master and then the communication stops. So, it could be like it can initiate one transfer and then multiple transfers can happen and then a stop happens. So, it could be for the multiple reads or multiple types between the master and state this is what happens ok. So, the master begins the communication by issuing the thought condition the 9 bit pattern is repeated is more best need to be calculated. So, this particular 9 bit ok 1, 2, 3, 4, 5, 6, 7, 8 data and then quantity ok. So, so first of all this technology is combined with this data because slave has to acknowledge that it has received this address and then I think we have to compute it like this. So, this constitutes the 9 bit. So, it is starting with this and then it acknowledges ok. A ok and then the next of the thing and then finally the stop bit is sent by the master to stop the communication. You know the number of bytes transferred is controlled by the master ok similar to any other bytes bus transfer. So, I stress the functioning and I stress the state can hold off the master in the middle of a transaction using what are clock searching. So, what happens is you know it is a device a slave device is low not able to consume at the far rate the master is pumping the data it can it can forcibly make the clock low. It does know when it is this acl or sda right this is the data bus and this is the data simple line and this is the clock the line it is connected to both the slave as well as the master ok. Both master and slave are connected to both of them both the lines ok maybe I will make it or. So, you see that the both lines are connected to both master and slave. So, master is driving the clock no problem let it drive it wants to, but when it is in the low if the slave holds it low for continuous for some more time the master even if it tries to drive it it will not be able to drive it to high because it is already pulling it to low clear it is all connected to the same line. So, this is the some kind of a communication that is the master saying that it is called you know flow control. So, to say that slow down your data ok I am not able to consume it in a way feed with which you are sending. So, it will do a clock searching to slow down the data transmitted over the. So, it will slow down until it is ready to continue ok. So, as you see protocol supports multiple master of course, the, but most system designers include only one master. So, normally there can be multiple master as I told you slaves can be many master can be one or more, but it says that a designer may decide to have only one master. Then the communication between any device between master and slave can happen and both can say you know read from or write from, but it is initiated always from master and the clock is also initiated from master ok, whoever is sending the data ok. So, there may be one or more slave on the bus. Both masters and slaves can receive and transmit data with each especially compatible hardware slave device comes with the predefined device as I told you any device connected to a bus can have a unique address, otherwise you will have to be able to communicate with the device. So, when it is manufactured then it comes to the unique address and then the lower which are which may be configured at the board level see what happens is may be I get an IP from one company they will have some slave device address, it is not like match where it can be unique 40 bit address is there and then we can read the case MAC address could be unique, but it may not be unique. So, what happens is at the board level, you know what we need is between the board or may be multiple boards if you are communicating with the devices which are there should be unique. We are not bothered if suppose another device in a different board has the same device ID as what is in this, because this is not going to be communicating with this device at any cost. So, no problem as long as the devices which are connected to the space to be I say bus in a single board or multiple boards which are connected to each other as long as they are having unique addresses we do not mind you know the same device addresses in the other board. So, that is why what is done is the higher bits are configured by their manufacturer may be and then the lower bits can be configured by the board developer. So, then you can get an unique address for each of the devices in a particular board. So, as this interface is a box interface such an interface between a microcontroller and the serial ICL bus. So, the interface is the you know between the arm ok arm SOC so, I said it is between the chips right the inter IC. So, that should be a controller within the chip it should be inside the chip and then it will drive on the bus ICL there is GA and SBL bit now pins will come out a CL and then they will be driven by the controller which will take care of which will understand the protocol. So, it could be called as a pipe physical level what it has to drive what moments of current and you know what are the addresses right. So, ICL three master features are clock generation. So, master has to generate the clock and start and stop generation because start signal and stop signal only indicates that the state that the data transmitted is number of bytes bytes transmitted how much has to be sent is controlled by the master. So, master sends the clock as well as the start signal and stop signal ok very simple handshake and easy to understand. So, slave features are programmable as per the address detection. So, when a particular master is driving the you know sending a particular device address the device should have slave device should be able to sample it and then find out whether it has been addressed. So, that detection address detection whether it is address which is coming on the bus is same as its own address that has to be that intelligence should be there and then that could be dual addressing capability that means the same device can have multiple same device addresses. So, if we behave like a mainly you know different functionalities each device address may be different. So, two slave addresses to the same particular device and then stop the detection it should direct the stop it. So, that know it it will know that the end transmission has happened in case know for even a by transfer or above transfer sorry above transfer. So, that is all now we say this really it is originally developed I say for communication between devices intelligent in that then example of simple I square decouple is called EEPROM thermal sensors and data block they are connected I square C EEPROM contains parameters needed to correctly configure a memory controller. So, memory controller is there ok memory controller and then it is connected through I square C EEPROM to EEPROM where you can put some information here which can be programmed also electronically from. So, based on data what is written into it on power on it can configure the memory controller. So, that how external memory devices can or you know internal M M you know memory main memory how these memories are to be configured that can be that parameters can be put in EEPROM because we need to store those values in the from permanent storage. So, it cannot be part of the memory just because we want to keep some configurable parameters we do not want to keep the whole memory or memory controller we cannot do that. So, we are providing a small EEPROM which will also be mapped on to some address ok it will be a it is it is not connected to ARM actually it is only on the I square C bus ok. So, if ARM wants to communicate it has communicate to the I square C bus ok because it has got only interface with the I square C. So, normally what happens is on power on this will come up and then it may configure the memory controller or it could be controlled by the program of the ARM and we can change the configuration also based on of the data. So, I square C is used for control processing devices that have separate applications to the data interfaces. So, we can have some interfaces to control processing devices the three devices that are for the devices which have a state C interface that can be connected. For instance this is commonly used in multiple applications where typical device include R of the video decoder mostly some audio or analog devices you know it is not a company name I am trying to any of the devices which you know with generation of signals you will say then they can be connected to the I square C bus ok. So, we saw one kind of a bus now let us see another standard bus that you may come across it is a serial peripheral interface it is called SPI let me give you some three instructions SPI allows ARM for full duplex synchronous serial communication signal device ARM for full duplex is what in a particular channel I consider it as a channel we have device one and device two in case of a half duplex what happens is only one communication is happening at a time but both it can be in both direction ok. So, half duplex is either at a particular time whether it will be D2 or be in a compartment at a point in time D2 will be communicated with a D1 but they cannot do it together that is for half duplex and full duplex means there is some other you know physical interface is available separate pins or separate lines so that this communication access this communication is possible simultaneously that is for full duplex and synchronous means it is the common clock is there and both the devices connected by a common clock so that they receive the data in synchronous with the sender ok so the interface can be configured as a master and in this case it provides the communication clock to the external so interface can be configured as a master then it is similar to what we call the SPI so master always drives the clock so it can be the interface is also capable of operating in multi master configuration in space C 8 or 16 the transfer frame format collection ok there we saw the 8 bit of data here 8 or 16 the transfer from the web for example data order MSB first or LSB so there we saw you know the order was fixed whereas here we we can decide to put MSB first or LSB ok in terms of time what is coming out of the first coming out part whether it is MSB coming out or LSB ok here LSB is coming out here may be you can say that MSB comes out in time 0 ok so that is programmable dedicated transmission reception flags with inter program so you can always say that on receiving one 8 bit data or 16 bit data inter the path so the controller can be programmed that way 1 by transmission and reception buffer with the DMA so it is a 1 by transfer either 8, 8 or 16 bit but the DMA capability is there that means you can transfer directly to memory from the device which is on the file device through DMA ok first signal master in play out data this thing can be used to transfer data in a play mode and receive data in a master mode so I said full input and half input then one may be sending and other way be receiving so same device can be sending in on one pin and then receiving on another pin that is going to fix mode so you can say that you know particular thing whether master is receiving or you know master in the play out this thing you can use to transfer data in play mode and receive data in a master mode ok it depends on the master when we derive in the block so the other person can other device will be accordingly looking at the data you know there are different pins available in the spiders in mode if I master out and slave in data this pin can be used to transfer data in a master mode and receive data in a slave mode so if if a device is in master and then this is play then which pin has to be used for a particular reception or so this is data is coming out ok coming in sorry master in this mi s open here it will be receiving the data ok and then it will be using mo f5 because it is sending the data here out ok so similarly on the slave side because this is a master so let me call it as a master so here slave device slave out so this will be connected to mi s o because this is the slave device this sending it out and then mo f5 will be receiving the slave in data so this is how the both are spiles compatible but the pins are connected like this so you will have communication that will be so clock will be driven by the master and input for it will be an input for slave play then this is an option to select a slave device so multiple again similarly to spy bus and xk3 multiple slave devices may be there and then you can select it to an nsf as to which slave device can be s1 is to slave device can be selected by the master to communicate let the spy master communicate with the slave induce union to over contents of the data so they can communicate over there so see here this is the clock driven by the master and then the bar actually decides the clock duty cycle what is the time we can see of this bar and then data coming in going out as to the parallel data parallel data is communicated you know translated into serial data it has to be transmitted okay ph buffer is a transferred buffer so it depends on so it is a master you know clock is going out so this is the master so master out is MOSI so this is the out so this transfer buffer comes here and then shifted out so if it is lsv first then lsv data goes out or it can consider msv goes out then so this data goes out similarly the data can also be received by this and then it will be coming in the receive buffer and then goes out it will be received by this state so there will be a logic here you know we will be considering using the memory map or may be you know it depends on how it is connected and then they will be configured using these registers what is the bar rate and whether it is input or output and then whether lsv first or msv first all these are all of different controls will be there it will be configured then the communication happens with all the devices and this is the send device select will be happy with me so let us about style interface now let us see what is the ESIR universal synchronous or single receiver it is also the flexible means of full duplicate data actually so u sort is always a full duplicate so there is a one pin txd rxd and then they will be communicating simultaneously you may have used serial port r232 in your earlier status so it communicates over a serial worker and then the ground will be there txd ok it will be connected to rxd and then if txd is connected to rxd so it is like a cross ok 7 and 2 and 3 so it is fine ground is required to know because this could be on a different voltage source and then this device could be on another voltage source so if they want to understand the signal which is being normally it is 7 and 12 or 15 so we need to have a common ground so there should be a ground connection also normally between them ok so it follows an industry standard no it is non returning to 0 that means the signal 0 or 1 is represented by minus value minus 12 volts and 12 volts is what is being normally followed ok so if the signal is never 0 even for a 0 communication suppose continuously if you are writing a 0 it will all be minus 12 volts so both the signal on the line will have some value ok it is not like you have 0 to 5 volts then if you are sending all 0 volts there will not be anything on the line voltage will be sensed on the line so you will not know whether all 0s are coming or neither nothing is granted so the receiver could get confused with the weight of voltage level on the bus so non return to 0 make sure that there is always some voltage level either positive or negative on the line so that the receiver could sense it and then find out whether if it is 0 it means nothing is connected if it is a plus 1 plus 12 it is a positive bits are being solved or if it is totally all negative this is it if it is a synchronous one-way communication and off-duplexing by communication transmitter clock output for synchronous transmission if you want a synchronous transmission it is asynchronous actually it can be asynchronous the transmission could be asynchronous or synchronous if you want a synchronous mode then there should be a process transmitter should also send a clock high speed data communication is possible by using a DNA so it is also DNA it can be in the case programmable data bits are 8 or 9 one way will stop it so what is the start and stop it you know so this is the time so this is the start bit normally it starts with some start bits and then data bits are different and then on stop it can be one or two bits bit so it can be configured you can see that for a 8 bit data 8 bit or 9 bit data this is one extra bit we are adding and then assuming that 2 bits are added as a stop bit then we are actually sending 11 bits for transmitting 8 bits of bits of data so this is the kind of over sketch value ok go ahead so we just separate enable bits for transmitter you can enable them separately you can enable only one of them you can detect receiver buffer tool see one byte is received then it will enter because it is currently at the serial data so it has to wait for complete byte to be received and it could be in terms of millisecond it may take millisecond of time but no processor is working and you know so it needs to wait for that particular 8 bytes one byte is received and then it will enter the processor to copy it from there so that next to the byte can be received from the serial code or a serial line so transfer buffer empty so what happens is processor writes the byte and then initiates the transmission and then it does not wait for the transmission to get over because it is sending it in serial code you know one by one one bit of time it will take a lot of time for that to be you know one byte of transfer data to be transmitted it will take millisecond by the time you know thousands of bytes of instructions can be executed by the processor so processor does not wait for transmission to complete transmission will be done and then once the all 8 are you know start and stop is everything you know 11 bits are sent then the user knows the character you know enters the processor so that next to byte can be written in the end of transmission flag so I know you can check this flag piracy control can be given no odd parity or even parity so what happens is if it is an odd parity suppose no you have 8 bit of data and then piracy which can be added to it so piracy can be odd bit option or even what happens is if suppose you are considering it for odd bit 8 bit of data 8 bit of data it could take any value 0 or 1 from some 8 bit data and then one more stock piracy bit is added to it suppose you use 8 bit data one more bit of piracy is added and if it is configured for odd bit odd number of ones are to be there suppose in the given data only 2 words you know rest of it is of 0 then it will put 1 here so that effectively the 9 bits are odd if you consider it for odd parity if it is for even parity it will be the reward so if it is only 2 1 it will put 0 as its parity or if it is the odd number of ones are there it will put a 1 more 1 so that it will be even so what happens is on the receiving side if the received piracy if it is set for odd parity suppose and then the receiver this is the receiver and this is the transmitter transmitter has taken care of sending 8 odd number of ones in the transmitted data into the data and piracy bit if on receiving side if it receives as an even number of ones that means there is an error that is one bit error has happened it can detect one bit error so it is a kind of an error detection mechanism it cannot hide the error because suppose one bit are changed from odd to even 1 to 0 or 0 to 1 you do not know which bit is corrected so it is not possible to correct this error which correction data correction is not possible but data error detection is possible because you will receive odd parity set so both transmitter and receiver should be aligned on it what parity is going to communicate with and then if it receives something different then you will know that there is an error so it is going to have a mark that tells you to send the data back so that kind of a parity checks can be done multi processor communication enter into new mode is address match is a multiple process is communicating over period mode then one of them should be in use because only one communication may happen here multiple transmission may not happen so all other devices can be new so that So, this is a very complex birth, you know the block diagram, I do not know where it will be to see it from forward distances. So, basically TX and Rx and then we have a transmitter power similar to what we saw in the spine. So, no shift register is there and then the bit has to be set out. Similarly, received data comes here and then it gets collected and then sent out data register ok. You have to wait for all the data to be received that before sending to the data register which will be you know on a APB bus ok. And then the bar rate you know what is the speed with which the bar rate needs to be aligned between the two devices ok. There is no clock between the in the arsenic mode. So, if there is in the absence of clock we have to have some means of pre you know before communicating it should be aligned ok. This is what is going to be my bar rate that means, is the receiver should interpret that 0 or 1 will take this amount of time in terms of second ok. So, whatever whatever means in terms of time how much is that you know bit bit. So, that it can wait for the clock to receive all the 8 bits or 9 bits of data which will be. So, that bar rate generation is one logic which is being actually done in this block. So, there should be a clock and then we have to pre note the value and then accordingly you know send out the particular bit in a particular speed. So, that can be controlled using this. And then if it has to be a synchronous mode suppose you want to communicate through synchronous mode then the clock will be driven by this circuitry which is connected to the other end of the device. So, the sampling and then clock rate bar rate generation is here and then interrupt can be configured using these registers. So, you can say transmit enable receive enable and then know on complete a transmit buffer mp interrupt as we generated or not all these things can be done using this part of the certificate. So, this is an high level overview of what is inside a an user clock ok. Then the last topic general purpose IO. So, it is very simple DPO is a generic screen on an integrated certificate whose behavior including whether it is an input or output screen can be controlled by a user at a friend's hand. So, DPO screens have no special purpose defined and go unused by default. So, you what happens in normally in a a chip ok the DPO screens come out ok. So, it will be called as 0 to know P 0 4 to 0 to 4 0 bit 1 ok to 7 and then there will be another 4 P 1 ok sorry P 1 P 1 4. So, we will have 0 to P 1 7. So, different screens are coming out this is actually individually can be configured as an input or output. So, it can drive a signal or may be you can connect to this LED then we can blink this ok whereas, in the simulator there are some brackets examples you can type out. So, this kind of a different based on the requirement of a system these screens can be configured. So, maybe in a some particular system you need only to input process lots of input. So, all the things provided can be configured as an input, but there may be possibility that you have only you want to output to come out of the chip which needs to be controlled on a many external security and the rest of it as an input. So, anything can be considered. So, the DPO is meant for such a kind of a purpose. So, we do not want to know freeze the number of input ports and output ports in the IC manufacturing itself. It is left to the programmer to configure it that is the purpose of this general purpose IO. So, it does not associate it does not come with some associated signal or something it is just a pre port it can be configured as an input or output. It is helpful to have handful of additional digital control lines that can be configured as input or output having these available from the chip. So, having these available type of instructions. So, so having these available which it can save the hazard having to arrange additional security to provide them it is part of a chip it can be done in software. So, features DPO can be configured to be input or output I told you that it can be detected you know selectively enable or disable it could be input values are readable ok. You can impact in the true software you can read a particular value you know suppose you are configured as an input unless you are able to read whether 0 or 1 is there under particular input line then there is no point in configuration right. So, the input can be read whether 0 or 1 output values can be write a value you can write a particular 0 or 1 into a particular thing and it will be dialed out a signal. So, it is very very very acquired for any embedded application input values can often be used as an IOR maybe you know we can drive the IOR typically for wake up behavior. So, some GPOs have 5 OS tolerant input ok. So, some chips are you know low voltage we know they are operating at 2 volts the GPIO pin levels are high voltage. So, they are like a ADCI told you that different way V reference is there which is a total difference from the supply voltage via IP even the GPIOs also have separate voltage which is much more than what is the operating voltage of the IP. So, this is a very helpful for a embedded applications where you want to interface this with some other device. So, use case scenarios to detect button cluster on the test system to receive interface from external devices or it could be this all if you are if you want to receive some interface if you want to send out some output it can be to build a LED or even buzzer how do you sound a buzzer because if you can change the frequency of this particular pulses going out on a film though you can only send 0 or 1, but the processor is running at a much higher rate ok. Please remember that it is in megahertz or you have explained. So, you can actually consider this pulses going out. So, then you can connect to the buzzer and then you can create this buzzer sound you may be change the frequency of this to generate different sounds along or anything you can be you can generate using the just GPIO output. So, but just changing it 0 to 1 and then in a particular frequency which is audible in the course. So, control power for external devices you can even control the power you know in this the internal can connect to another red light or something which will you know operate and relay will operate and then it will be there and you can control the power given to the another devices. So, with this we have come to the end of this session ok. We have discussed a lot about different kind of protocols and the serial both device and a generic cross-sample purpose idea. So, having seen these devices and maybe having understood some high level features of them I think you will you are in a better position now to look at the manual of a particular source that you have ok. And what are the peripherals and what kind of communication happens now you will have better idea of what is being given in those kind of manual ok. My intent is to give you a overview so that you are comfortable reading those documents to know more output because these are all implemented all these are all implementation specific. No, I cannot say that in a particular register you know if you change this D 0 bit you know it will short transmitting you know it is depends on which tip you are looking at and what implementation with company it is from. So, it is all very implementation specific that is why I did not go in the details of you know registers and similar to what we went through in ARM instructions. But it is you know very much required that you understand the philosophy and how does it operate so that you will be able to appreciate when you come across devices in your design problems or when developing software was embedded system. So, hope this the discussion was very useful and I really enjoyed sharing this information with you wishing you all the very best and let us see in the next session to talk about different feature families and later families of ARM processors and what are the high level features that are supported in them ok. Thank you very much for your attention and your support and it has been a great wonderful time sharing it to you in the next class. Bye bye.