 Hello, and welcome to this presentation of the STM32 General Purpose I.O. interface. It covers the general purpose input and output interface and how it allows connectivity to the environment around the STM32 and microcontroller. The general purpose I.O. pins of STM32 products provide an interface with the external environment. This configurable interface is used by the MCU as well as other embedded peripherals to interface with both digital and analog signals. Application benefits include a wide range of supported I.O. supply voltages as well as the ability to externally wake up the MCU from low power modes. General Purpose I.Os provide bi-directional operation, input and output with an independent configuration for each I.O. pin. They are shared across up to eight ports named GPIO-A to GPIO-H. Each of them hosts up to 16 I.O. pins. I.O. ports support automatic bit set and reset operations through BSRR and BRR registers. I.O. ports are directly connected to the AHV-2 bus in order to allow fast I.O. pin operations capable of changing every two clock cycles. Most of the I.O. pins are 5-volt tolerant. General Purpose I.O. pins can be configured for use in several operating modes. An I.O. pin can be configured in an input mode with floating input, input mode with an internal pull-up or pull-down resistor, or as an analog input with optional pull-down. An I.O. pin can also be configured in an output mode with a push-pull output or an open drain output with an internal pull-up or pull-down resistor. For each I.O. pin, the slew rate speed can be selected from four ranges for the best compromise between maximum speed and emissions from the I.O. switching and to adjust the application's EMI performance. I.O. pins are also used by other embedded peripherals to interface with the external environment. Alternate function registers are used to select the configuration for the peripherals in this case. The configuration of the I.O. ports can be locked to increase robustness of the application. Once the configuration is locked by applying the correct write sequence to the lock register, the I.O. pin's configuration cannot be modified until the next reset. Several integrated peripherals such as the Usart, Timers, SPI, and others share the same I.O. pins in order to interface with the external environment. Peripherals are configured through an alternate function multiplexer, which ensures that only one peripheral is connected to an I.O. pin at a single time. Of course, this selection can be changed while the application is running through the GPIOX, AFRL, and AFRH registers. The configuration of any I.O. pin is achieved through four 32-bit registers GPIOXMODER GPIOXOTYPER GPIOXOSPEDR GPIOXPUPDR Registered GPIOXMODER selects the functionality of the I.O. pin. Install input, digital output, alternate function, or analog. Registered GPIOXOTYPER is relevant when the pin is an output. It selects open drain versus push-pull operation. Registered GPIOXOSPEDR selects the speed of the signal received or transmitted by the pin, and registered GPIOXPUPDR enables or disables pull-up or pull-down resistors whatever the I.O. direction. During and after reset, the alternate functions are not active. Only debug pins can be used in alternate function mode. JTAG serial wire debug or SWD pins remaining in alternate function configuration mode are listed in this slide. When the external oscillator is switched off, pins related to this oscillator can be used as standard I.O. pins. This is the default state after a device reset. When an internal clock source is used instead of a crystal oscillator, only the related OSC-IN or OSC-32-IN pin is used for the clock, and the OSC-OUT or OSC-32-PIN can be used as a standard I.O. pin. The pH-3 may be used either as a boot pin, boot zero, or as a GPIO. Depending on the NSW boot zero bit in the user option byte, it switches from the input mode to the analog input mode. After the option byte loading phase, if NSW boot zero equals one, and after reset, if NSW boot zero equals zero. So the pH-3 pin is not a dedicated pin. It can be used during reset time to select the boot mode, and can become a general purpose I.O. during runtime. Each I.O. pin of the GPIO port can be individually configured as secure when the trust zone security is active. Trust zone security is activated by the TZEN option bit in the Flash OPTR register. When the trust zone security is active, the configuration bits of a secure I.O. are secure against any non-secure access. Secure I.O. data cannot be redirected to a non-secure I.O. Non-secure I.O. data cannot be directed to a secure peripheral. If an I.O. is secure, it can be accessed by non-secure and secure digital peripheral, and only by secure analog peripheral. If an I.O. is non-secure, it can only be accessed by a non-secure digital peripheral and by a non-secure analog peripheral. After reset, all GPIO ports are secure. I.O. pins remain active in all modes except standby and shutdown, where the only available configuration is input with internal pull-up, pull-down resistor, or floating input. When exiting shutdown mode, the I.O. configuration is lost. When the MCU is under reset, I.O. pins are forced into an analog input mode.