 Welcome to the video lecture on universal shift register. After the end of this session, students will be able to describe the working of universal shift register and they will be able to implement n-bit universal shift registers. So, before moving towards concept, you have to recall the basics of shift registers like CSO, CPO, PSO and PPO that is the basic modes of operation and bidirectional shift register concept. So, let us move further. So, the universal shift register is nothing but the type of shift register having both the shifts and parallel load capabilities means it is a kind of bidirectional shift register in which the input can be given parallely or serially and the output can also be taken in parallel or serial form. Depending on how many number of flip flops we are using in that design, we can call it as n-bit universal shift register. For example, if we use 5-bit flip flops, then we can call it as 5-bit universal shift register. So, this is the logical diagram of 4-bit universal shift register. Here you can see that 4-bit flip flops are arranged in a specific manner with the multiplexers. The design can be realized using this 4S to 1 multiplexers. The output of multiplexers is given to the corresponding d-flip flops. Here the two select lines that is S1 and S0 are the select lines which are common for all the flip flops. Means if we want to select the input 0 of all the mugs, then we have to set S1 and S0 as 0 0. If we have to select the input 1 for all the mugs, then we have to select S1 as 0 and S0 as 1. If we have to select the input of multiplexers 2, then we have to make the S1 is 1 and S0 as 0. If we give the input S1 and S0 1 1, then we can select the input 3 of the corresponding multiplexers. Now, whatever input we have given, that input is taken as or the output is taken to the input for flip flops d. Here I3, I2, I1 and I0 are nothing but the parallel inputs for the corresponding multiplexers and A3, A2, A1 and A0 are the parallel outputs. Here as it is synchronous circuit, we have to give the common clock to all flip flops and the clear connection is also common. Now the serial input for shift left shift right resistor is given to the first multiplexers input 1 and the serial input for the shift left resistors is given to the last multiplexer at pin number 2. So, let us see the different modes of operation according to the select lines S0 and S1. This is a mode control that is the, it will decide according to the S1 and S0 inputs, the resistors operation, so first if we give 00, then there will not be any change at the previous state output, means the next state output will remain same. If S1 is 0 and S0 is 1, then it will be in shift right operation mode. If S1 is 1 and S0 is 0, then the universal shift resistor will be in shift left operation and if both are 11, then it will be parallel load operation. Let us move further. So, first we will consider the case S1 and S0 is equal to 00. So, before going to the outputs, we have to trace the path between multiplexer and D flip flops for the input and outputs. So, it is indicated by dark purple lines. So, you can see here the output of flip flop D that is first D flip flop that is A3 is given as the feedback to the corresponding multiplexer 1 at the pin number 0. As we have selected S1 and S0 as 00, so the same output is fed to the multiplexer and its output is fed to the D flip flop as the input. So, at the first clock pulse, the same output will be generated. Then it is a case with the second D flip flop and corresponding multiplexer, it is similar case with all remaining flip flops, means the same output is fed back to the multiplexers, by default it is input for D flip flop. So, the output will be remains same at the each and every stage as we give the clock pulses. For example, if we consider we have to give the input 1011, then it will remains the same in that condition 1011 until S1 and S0 are 00, means whatever the output that same will be fed as the input and we will get the same output. Now next condition is S1 and S0 is equal to 01, means S1 line is 0 and S0 line is 1. So, what should be the path? So, the path is indicated with the dark black line. As you can see here, due to S1 is equal to 0 and S0 is equal to 1, all input ones are selected by the multiplexers. So, we can trace the path like it is a serial input for shift right register, it is given as 1 and the corresponding output of D flip flop is given as input to the next D flip flop. The same output of the next D flip flop is given as same output of the D flip flop is given as the input to the next MUX, like that the output of D flip flop is given to the next MUX and by default next D flip flop means here the shift right operation is performed. For example, again we will take 1011 data is to be transferred with right shift mode. So, at the first clock pulse, the 0 will be the input for MUX. At the next clock pulse, this 0 is transferred to right side by 1 bit and new bit will be appeared at the first multiplexer that is 1. Then in the next stage, again the data is shifted towards right with 1 bit, thus at the last clock pulse we will get output 1010, this is shift right operation. Now, if we consider S1 and S0 as 10, so here the pin number 2 of all the multiplexers will be activated or it is selected, then we have to see from the rightmost flip flop. The output of this flip flop is given to the input of the next or previous multiplexer. The output A1 is given to the previous multiplexer and output A2 is given to the previous multiplexer and corresponding outputs are given to D flip flop as a input means here the left shift operation is done. For example, again we have to give 1010 format, then we will start with leftmost bit 1. So, first input will be given to the last multiplexer that is 1. At the next step, the bit is shifted towards left that is the data of A0 will appear at A1 and the new bit will appear at A0. In the third clock pulse, the output will be 1010 and at the last the output will be 1010. Now, we will see when S1 and S0 is equal to 1. Here the dark red line indicates the path I3, I2, I1 and I0 are the parallel inputs and A3, A2, A1, A0 are the parallel outputs. Here only two clock cycles are required to feed the data in D flip flop and to take out the data from D flip flop. So, first the first clock cycle will load the data from I3, I2, I1 and I0 simultaneously as we have selected the pin number 3 with S1 and S0, 1, 1. The data will be given to D flip flop and similarly at the second clock pulse, the parallel outputs can be given, can be taken out. So, this is the data 1010. At the next clock pulse, we can collect the data simultaneously. So, this is the operation related to parallel input and parallel output. So, pause the video for while and think about if we want to use the universal shift resistor as a buffer, then which mode of operation will be selected? Okay. So, the answer is we have to select S1 is equal to 1 and S0 is equal to 1, that is parallel load operation. These are some applications of universal shift resistor which is used for up-down counters, time delay circuits, calculators, scanning circuits and these are the available ICs. So, the 4-0 series will indicate 4-0, 1-9-5 is 4-bit universal shift resistor, 7-4-HC, 1-9-4 and 7-4-HC, 1-9-8 are 7000 series of the universal shift resistors. These are references. Thank you.