 अच्टलाम लेक्म श्टूडन्च, आम वसेमी क्राम, this is the 20th lecture in a series of 45 lectures on digital logic design. कैसे हैं आप चला अच्टले होंगे. पिशन लेक्चर में हमने बाच रूगी ती, programable logic devices से, PLDs से. PLDs जो है काफी इनका एक रोल है, modern logic design में. आम ने जेज्चचन श्टाड की ती, D-Multiplexers से. D-Multiplexer भीसेकले हमने काथ एक फुँट्शनूल जूनेत है, फुटशनूल दिवाईस है, and one input is multiple outputs. यह स्वोचन लेक्चर मुल्टीपल डस्पनेशनजन जाएं. तो आप कोई भी अुट्ट्ट सलेक कर सकते हैं, और देटा अनपुट पे रूट कर सकते हैं, किसी भी अुट्ट्ट पे. तो आप प्लिकेशन श्टी की ती, एक तो यह के आपका जाए से A-L-U है, उसका अुट्ट्ट चो है, उसके अुट्ट पे जो भी रूट आर है, वो दिफ्ट आपने रेजिस्टर्स में, यह मम्री उनेट्ट से श्टोर करनें. तो एक तरीका तो यह कभ दी मुल्टी प्लेक्सर लगालें, उसके अुट्ट पे जो भी वैलिए हो आगी, वो किसी भी अुट्ट पे बहीज सकते हैं. तो अुट्ट पे जो भी मुल्टी प्लेक्सर के वो दिफ्ट रेजिस्टर्स के साथ कुनेट रेजिस्टर्स हुँट वोने. तुसी हम नहीं आपने एक प्लीखेचन जो स्टडीग ही ती. वु ती सीरिल नहीं जो आगी नहीं जो आगी तो उसको पलल में कनवरट कर ना. उसे बेसक्ली आप ये प्डी मुल्टीप लईक्सर्च मुली के नेंगे वूगते आन्पृह्य Unknown जार दिखन ताइप्स की हमने PLD दिवाँसे से दिखस केती, पैली जो ताइप ती P-ROM ती P-ROM ती P-ROM बल राम उसक हमने ये बतायता है, के जो AND गेट अरे है, वो पले से P-PROGAMED है, और उसको D-CODER के तोर पे P-PROGAMED की आवाई. तो जो युजर है वो संपली उसके और गेट अरे जो उसको प्रोगाम कर सकता है, और P-ROM जो है वो आज अन अप्लिकेचन को एक दिवाइस के तोर पे अस्तमालनी होगा, उसके एक खास मक्सध है, वेसेखले ये तोर जो प्रोगाम, P-ROM को हम बाद में भी देखेंगे, उस से प्रोयाइistles कмотритеरे मोगना भी उन्षे सईक्त तुर प्रोगाम प्रोगाम टिदटे। अस्ते वहाँ ब् Laughs पाशगे सवठे आप प्शिवाँबो आप प्शिवाँबो बालेगम देवाचार ढ्गी बानी कुचाईःस्तिःकैचीः स्नदिखेँदेगाश्टुगेगेदेहगेगेगेगेगेपाःदुचाउटुदुचाउटुटुचाउटुचाउटुच तीसीडी यो अप्टन ती जो है और गेट का अट्बृट है, उसकों अकेट ऱा मैं, आखटिट आई पना सक लह, यह लिए शवर लिए आए, उसके विटा थी अप्टन कों क्ये इस ते धिन आए अप्टन किट ती आए, एसके यह आपकी अअप्टन किलगे आए, गिन और अमने एक इजमपल देखी दी जिसके चार इंपोट थे, त्री अधबबट थे, और चे प्रोडिक तम्स हमें में में रही थी. शो इस से हम दिफ्रन्ट फुंक्षन्स प्रगाम कर सकते है, अपने इजमपल भी देखी ती, अध प्राँम नमबर चैकर सरकत बना आपता वो फुँँ प्रगाम कर गे देखेंगे प्ले तीवाईस से. अगर आप को याद हूँ बूलिन आजब्रा के रूल्स जों है, आपके पास एक आन्द गेट है, उसके दो आप इन्पुत है, एक पे वीरीबल ए खुनेक्रिट है, तुस्रे पे ए बार खुनेक्रिट है, उसका अपुत क्या आएगा, बीसिकली जीरो होगा, अगर बूलिन � उसम्ती अन्गेट ने अगर भागत सार और बागत खुनेक्रिट है, अगर ःूँ yoga यह आलेक ले के अधूटर्ट पिया उडिलो जाएगट तरयेगा यह थो पड़िक ताम है यह गर दरीग होगा, off course zero आएगट के ऐसात बएका तो आगया उआग आप दूटर्ट के आप तो पर इट हैगा आप सईह रहे थो गड़ को आएगट के आप पडिलो त सुनग सूभ अद प्रीम नमबर जगर है, उसको कैसे अंपलेमेंट करने, using the same 4x3 PLA. Let us have a look at a 4x3 PLA device, which is programmed to give constant 0s and 1s. Let us look at the first AND gate, which produces a product named P1. All the inputs to the first AND gate are connected. So, the inputs to the first AND gate are I1, I1 bar, I2, I2 bar, I3, I3 bar, I4 and I4 bar as shown by the fuses. So, the output of the first AND gate P1 would be 0. Now, to obtain a 0 at the output of the PLA device, the first OR gate having the output O1 is connected to the product term P1. Therefore, the output of the OR gate is going to be a 0. Another way to obtain a 0 output would be through OR gate 3, the third OR gate, which has an output of O3. Now, as can be seen in the diagram, the third OR gate is not connected to any of the six product terms. What is the output of the third OR gate? Basically, it is a 0. Now, how do we obtain a logic 1 at the output of the PLA device? Looking at the second OR gate, it is connected to the product term P2. Now, looking at the inputs of the second AND gate, the inputs are disconnected. So, none of the fuses are intact. Therefore, P2, the output of the AND gate P2 would be a 1. The second OR gate is connected to, of course, the output of the second AND gate. Therefore, the output of the OR gate would be 1. We have just looked at the programming of a PLA device to give us constant zeros and one outward. Now, let us look at a more practical application. Last time, we had read a lot of lectures, the odd prime number checker circuit. In the odd prime number checker circuit, we applied a 4-bit input. So, from 4-bit inputs, you have numbers from 0 to 15. Basically, you have designed a circuit which checks the 4-bit input number. If that 4-bit input number represents an odd prime number, what was the circuit output? It would be 1. Basically, you have to implement the same circuit using the 4-3 output PLA. Now, if you look at the PLA, how many product terms do you have in it? Basically, you have 6 product terms because you have 6 AND gates. Now, if you recall the Boolean expression which you had written for the odd prime number checker circuit, the odd numbers in it are basically representing the min terms of 1, 3, 5, 7, 11, 13 and so on. So, these are the min terms. If any of these terms are there, the function output would be a 1. Now, how many prime numbers can we check with this 4-3 PLA device? Basically, we can detect 6 prime numbers because we have 6 product terms to implement. If we had more AND gates, of course, we could check more prime numbers. Now, let's talk about how implementation will be. Basically, the first AND gate whose product output is P1, what will it detect? It will detect product term or min term 1. Similarly, what will the second one detect? Basically, the second min term which is 3, the second prime number, it will detect it. Similarly, we have to configure the remaining 4 AND gates so that they detect min terms 5, 7, 11 and 13. Now, what should the output of this PLA be? If you look at the first AND gate, it should be output 1 whenever we have a prime number, basically, an odd prime number. So, the first AND gate, its inputs will be connected to the 6 products you have. Okay. What are the other 2 AND gate outputs done? Basically, you leave them unconnected. They do not have such use. But since we have 3 outputs, let's just make use of the remaining 2 outputs. We do that on the second AND gate, we say that multiples of 9 should come to us. So, what will the multiples of 9 do? 1 and 3 will come. And on the third output, we say that multiples of 39 should come. So, multiples of 39 will come in 13 terms and some other terms will come. So, let us have a look at the implementation of an odd prime number checker circuit using the PLA. Let us have a look at the implementation of an odd prime number checker circuit using the 4 into 3 PLA device. Now, looking at the first AND gate which gives an output P1, the inputs are i1, i2 bar, i3 bar, i4 bar. This represents the minterm 1. Looking at the second AND gate which gives a product output P2, it is connected to the inputs i1, i2, i3 bar, i4 bar. Basically, this represents the minterm 3. Now, looking at the third AND gate which gives a product output of P3, it is connected to the inputs i1, i2 bar, i3 and i4 bar. This represents the minterm 5 which is again another odd prime number. Looking at the fourth AND gate which gives a product term P4, the inputs are i1, i2, i3 and i4 bar. This represents the minterm 7. Looking at AND gate 5 which gives an output P5, the inputs are i1, i2, i3 bar, i4. Basically, this represents the number 11 or the minterm 11. Now, looking at the last AND gate which gives an output P6, the inputs are i1, i2 bar, i3 and i4. This represents the minterm 13. Now, the first OR gate which has an output of O1, this gives the output of the odd prime number detector circuit. So, if it detects any of the 6 prime numbers, the output should be 1. So, as can be seen in the diagram, the 6 inputs of the first OR gate are connected to the 6 product terms P1, P2, P3, P4, P5 and P6. Now, considering the second OR gate, second OR gate is connected to product terms P1, P2 and P3. Where are the three terms? Basically P1 represents minterm 1, P2 represents minterm 3 and P3 the output represents minterm 5. So, basically the output, the second OR gate output represents multiples of the number 15. So, multiples of number 15 are 1, 3 and 5. Similarly, looking at the third OR gate, the third OR gate is connected to product terms P1, P2 and P6. So, what do product terms P1, P2 and P6 represent? P1 represents the minterm 1, P2 represents the minterm 3 and P6 represents the minterm 13. Now, all these three terms are multiples of the number 39. So, basically this 4 into 3 PLA device has been configured to output three different functions. The first OR gate detects an OR prime number. The second OR gate or the second output detects multiples of the number 15 and the third output detects the multiples of 39. We have looked at a very simple example of the implementation of an OR prime number checker circuit using a 4 into 3 PLA. If you have a big PLA which means more product terms, more inputs and more outputs you can implement bigger functions. Now, let us have a look at the generic array logic GAL device. GAL device, if you remember, we talked in the show that its AND gate array can be programmed and the OR gate array can not be programmed. This GAL device is different from a PAL device in two respects. One is that you can program it again and again. You can not change the PAL once you have programmed it. In GAL device, you can program the AND gate array multiple times. If your function is not properly programmed, you can program it again. If you want to modify a function that you have implemented, you have the option. The second feature is that you can configure the outputs which are not in other devices. There is a capability in this that you can program the AND gate array multiple times. How is that in this? Basically, it does not use fuses. In this, E-square CMOS logic is being used. There is a circuit which we will call electrically erasable CMOS. So, at each junction, basically as we talked in the show, you have a vertical set of lines and we also talked about that every horizontal line is connected with every vertical line through a fuse. So, whatever you have to program, either you let it be or blow it out. What will happen in this? Basically, at each junction, the horizontal line junction has an A-square CMOS cell which you can program. So, if you have to connect that cell, then your vertical line will be connected. If you have to disconnect that cell, then you have to turn off that cell. So, basically, if you have to program a logical function in AND gate, then it will turn on corresponding cells. The other cells will turn off that cell. So, let us have a look at the structure of a Cal generic array logic and we will see the other example of how it has been programmed. So, let us have a look. Let us have a look at simplified architecture of a GAL device, a generic array logic device. There are four inputs. Basically, A input, A bar input, B input and B bar input shown by vertical connections of vertical lines. There are three AND gates. Of course, this constitutes the AND array which can be programmed. The outputs of the three AND gates are connected to a single OR gate. This represents the OR gate array which cannot be programmed. So, as can be seen in the diagram, the outputs of the three AND gates are permanently connected to the OR gate. The output of the GAL device is the output of the OR gate which is X. Now, at each junction of the vertical line and the horizontal line, you see a cell with E square CMOS. So, let us suppose the first AND gate is connected to implement the function AB. So, how do you do it? Basically, you would turn on the first E square CMOS cell in the extreme top left corner and B would be connected by turning on the cell in the second row third column. Let us actually program a GAL device. The first AND gate is programmed to give a product term AB bar. So, as can be seen in the figure the first cell and the last cell in the first two rows are turned on the remaining cells are turned off. Similarly, the second AND gate gives out a product term AB. So, in the third row and the fourth row, the second cell and the third cell are respectively turned on the remaining cells are turned off. So, the product, the output of the second AND gate is AB. The third AND gate gives an output AB. In order to implement this the fifth and the sixth rows have two cells which are turned on the first cell and the third cell which are turned on the remaining cells are turned off. The output of this GAL devices of course, AB bar plus AB bar B plus AB. We have just looked at a simple implementation of a GAL device we have also programmed it a simple SOP function we have programmed it. Now, let us talk about the outputs of the GAL device. GAL device we have told that it is different from the PAL device because we can configure the outputs. So, its output is a little different from the PAL device basically, the output circuit is separate, we call it logic macro cells. So, we are going to have a look at the circuit diagram. So, each output is represented by a block which is known as an output logic macro cell or ALMAC OLMC In this OLMC an OR gate will be part of the OR gate array and some extra circuitry. We can configure that extra circuitry so that we have different output terms In the beginning, if you remember we talked about the outputs of the GAL device so that they can act as inputs how that will happen by programming the output circuit the OLMAC. So, let us see the block diagram of the GAL device in which the OLMACs are shown separately. Before we have a look at the circuit diagram there is a small thing how to identify basically, identification is very easy again, its prefix is GAL after that there will be a number let us say 22 22 indicates how many total inputs and outputs we talked about the outputs of the GAL device so 22 means perhaps some inputs and some outputs which can be programmed after that, you will get a letter V which means the output can be programmed after that, there will be another number let us say 10 this indicates the number of outputs so the ID of the GAL 22 V 10 similarly, there is another GAL device where the inputs are different and the outputs are different 22 and 10 will be different the block diagram of the GAL device which shows the AND gate array and the output logic circuits macro cells OLMACs the block diagram of the GAL device is shown if you remember, if you compare it the block diagram we saw is slightly different we are showing an E-square CMOS programmable AND array basically, this array all the E-square CMOS cells which we can program and configure the output AND array is connected with OLMCs which is output logic macro cells so every OR gate array each OR gate will be in each OLMAC so let us say 10 outputs of GAL device 10 OLMAC circuits and 10 circuits of multiple inputs as we said you can configure OLMAC so the output can be changed in the input and the input can be feed in the AND gate array the input of GAL device will be connected to AND gate array as shown in the diagram input 1, input 2, input n the outputs are from OLMAC outputs from output 1 to output m till now we have concentrated on different devices architecture how they are connected how they are programmed till now we have not talked about actual programming how they will be done basically programming is very simple programming is done the way you are programming to do programming you need a compiler of a language like C compiler like FORTRAN similarly to do programming you need a compiler you need a language in which you will write the function of a device there are different languages the languages which are used are called hardware descriptive languages called HDL different types of languages are available we will concentrate on ABLE ABLE is basically in which ABLE is referenced we will study it ABLE is an acronym for Advanced Bullion Expression Language okay now the thing is how to use this language if you want to program any function let's say odd prime number what you have to do first you have to tell the function any combination circuit how you will represent it basically there are two ways one is to write a bullion expression bullion equation what can be the other way basically there can be a truth table any function let's make it a truth table let's specify its inputs let's specify its outputs so if you specify the truth table that means there is complete information how to represent a function that is basically state diagram we will study state diagram basically there are two types of circuits combinational which we are studying and a sequential circuit in which there is a memory element to represent sequential circuits we use state diagrams when we will read it later we will see it again so basically there are three ways to represent a circuit one is bullion expression if you have represented a function after that basically what you have to do let's say you write a program in C after writing basically you compile it before compiling before compiling you see are there any errors basically the compilation process shows you the errors here also you have to do the same when you have represented a function you have to see the errors there are no syntax errors there are no bugs you have to debug them when you have done that after that you have to test it what you have told the function through a truth table you have to test that function because test is really important because let's say you have PROM or PAL we talked about it when you will do the program after that if there is any mistake then the device will be useless again you have to program with a new device so it is important that you have to test any function how to do the test basically the second step is called test step you will make a test vector what is the test vector let's suppose you have implemented an exclusive OR gate using PAL device 2 input exclusive OR gate what possible combinations 4 possible combinations so if you are told to test an exclusive OR what you will do you will apply the 4 possible combinations you will see on its output if the output is coming properly corresponding to every input that means your device is working fine you have defined its boolean expression or truth table so similarly you have to make a test vector that means you have to apply your programming language the compiler you are using will test that function if its results are verified that means your function which you have defined which you are trying to implement that is fine you can go to the next step what happens in the next step basically all this information is compiled and it is represented in another form the output of the compilation will be a document file in which you have defined the function or the truth table all that information will be there and a fused file will generate an output basically this is the file which you can directly program any PLD device now the programming language which we talked about was basically device independent in which it will not be let's say you have to program or PLA or GAL for that there will be other languages there will be only one language basically it is supporting all basically this is the language it is device independent you have given the information it will be compiled you will have a document file a fused file how to program you should also have a PLD device it will be a plugin and you will download the information through the computer to the device programmer so the device programmer whatever device is in it will be programmed so the complete system which you want to program for any PLD device you will need a device programmer which will be attached to your computer you have to add the information you have to compile the fused file or the fused map which will be downloaded on the device programmer whatever device is in it it will be programmed we will see all these steps in detail actually we will try to implement a function and we will go through all the steps let's come back to GAL devices one of the popular type of GAL devices which are commonly used we will study them we will see their structure in detail basically the first device we are going to study is GAL22v10 22v10 tells that the total inputs and outputs can be biased basically there are 12 inputs of this device 10 outputs which you can configure as inputs therefore you have 22 and all the outputs you can configure them to provide you with different outputs in this device so in different configurations it means that it is available in different voltages 3.3V 5V secondly you can program this GAL device and put it in a circuit any application after that if you want to modify it and reprogram it you don't have to remove the GAL device you have a proper interface which is directly connected with the GAL device in that circuit board and you can program it while keeping it in the circuit so this is providing a lot of flexibility now to describe this GAL device GAL22v10 it is a little difficult so let us have a look at the slide before we have a look at the slide there is one important thing there are 10 outputs so every 10 outputs are coming from an ALMAX as we have told in every ALMAX there is another gate now this GAL22v10 device it has different product terms which are connected with different ALMAX so there are 10 there are 8 inputs 2-10 2-14 and 2-16 so let us see the different product terms where they are connected let us have a look at the circuit diagram of the GAL22v10 PLD device it has 12 inputs shown by the 12 input pins one of the top pins it has an oblique clock so it can be used as input and it can also apply a clock signal which we talked about about sequential circuits it is used in that, there is a clock which we will see later when we study sequential circuits E-square CMOS programmable AND gate array where the AND gate array is which we are programming and each cell is implemented by E-square CMOS this AND gate array the inputs are through input buffers so each input has an input buffer so the input is complemented or non-complimented the form is connected with AND gate array so if we look at the inputs there are 12 inputs so these are going to 24 inputs AND gate array let us have a look at the output you can see 10 outputs which are connected to 10 ALMAIC circuits the different inputs and outputs of ALMAIC circuits if we look at the first one there is an input on which slash 8 is written basically this input is coming from AND gate array 8 product terms are coming which are connected with an 8 input OR gate the OR gate is already in ALMAIC similarly an output is going back to AND gate array this basically if you configure the output pin as input so this input is going back to AND gate array so this output you can see a buffer which is going back to AND gate array it is doing the same similarly if the output can be sent back to input it is also sent through this on the output of ALMAIC you can see a tri-state buffer which you can control, enable and disable similarly if we look at the second ALMAIC there are 10 inputs i.e. 10 product terms are coming so the OR gate in this ALMAIC will have 10 inputs similarly the third ALMAIC has 12 product terms 14 is coming in the fourth 16 is coming in the fifth 16 is coming in the sixth so there are 10 ALMAICs there are 8 products of 2 2 of 10, 2 of 12, 2 of 14 and 2 of 16 there are 2 more signals on the input of this ALMAIC there is a clock signal this clock signal is common from all ALMAICs so one clock is controlling all ALMAICs internal circuit again when we read the sequential circuit we will see it again another common signal that is a reset signal the output signal on the top right hand is basically a reset signal which is controlling all of them we have just seen the circuit diagram the GAL22V10 device it has a very complicated view you don't have to worry about it we will simplify it and we will keep on watching and then it will be easy to understand it one important part of any GAL device is the output circuit ALMAIC as we mentioned earlier we can program it to provide us with different options we can get some function output or we can configure the output pin as input or we can connect the output with the AND gate when we talk about sequential circuits we can store the information that is the facility so let us have a look at the ALMAIC circuit actually what it is doing and how we can configure it or program it basically we have 4 options there is a combinational mode which is used in combinational circuits and there is a registered mode which is used for sequential circuits because we have read combinational circuits so we concentrate on combinational mode we will see the registered mode later we will see the registered mode later so let us have a look at the detailed circuit of an ALMAIC and let us study how we can configure the circuit to give us different options let us have a look at the circuit diagram of the output logic macro cell or ALMAIC circuit you see different components the input is through the OR gate the input to the OR gate is from the programmable AND array the output of the OR gate is connected to a flip-flop flip-flop is the sequential device which we have repeated later we will do when we will read sequential circuits basically the flip-flop is a memory element one bit information which can store it the output of the OR gate is connected with a multiplexer we have a 1 to 4 multiplexer which has 4 inputs 2 select inputs S1 and S0 the output of the OR gate is connected with input 3 and input 2 similarly the non-inverted output of the flip-flop is connected with input 1 and the inverted output is connected with 0 input the second one is connected with 1 to 2 multiplexer which has 2 inputs 1 select input S1 the input 0 is connected with the complemented output of the flip-flop and the input 1 is connected with the output of the tri-state buffer the output of this multiplexer is connected with an input buffer the output is connected with complemented form or uncomplimented form and gate at the input let us look at the tri-state buffer as i told you you can activate it and deactivate it through a control line the control line is coming from above where it is written let us suppose the control line of the tri-state buffer if we activate it then the tri-state buffer will start working as a not gate it will invert the input and give it an output and if we activate it and enable the line then the tri-state buffer will not work basically it will disconnect the output on the extreme right side you can see a pin where i and o are written but we can configure it as an input pin now let us have a look at the two configuration modes of the all-max circuit as i told you earlier there are four different options for programming it there are two combinational modes we are looking at two combinational modes the first mode is combinational output with active low the second mode is combinational output with active high if you select the third input on S1, S0 which selects the third input of the multiplexer then the result is the output of the gate will come on the output of the multiplexer in an uncomplimented form because it is inverting so the output pin will give the output in inverted form combinational output with active low output the second option combinational output with active high if you select S0, S1 select the second input of the multiplexer then what will come on the output basically the output of the gate will be inverted and the output of the multiplexer will be inverted again and the output pin will come now this information will be exactly the same which is on the output of the gate so it is coming in a non-inverted form we will call it combinational output with active high output the second mode the registered mode the flip-flop which we can see will be used we will not discuss it let us have a look at the tristate buffer circuit we are using this circuit basically it is a not gate which we can control through a tristate control pin so if this is high so the information on the input will be inverted on the output as you can see in the diagrams the control pin is set to high if you apply high input at the input of the tristate buffer it is converted into logic low similarly if you apply logic low then the output of the tristate buffer becomes high impedance high impedance means high resistance high resistance only when there is an open circuit so basically if the control pin is low then the output of the tristate buffer will be open basically where do these tristate buffers are used they are used in the tristate buffer the output of the tristate buffer where do tristate buffers are used it is used there where many circuits outputs are connected on a common point let's suppose there are 4 end gates one end gate is giving 1 the other one is giving 0 if you connect the outputs of these 4 then you won't know what value will come one gate is giving 1 the other two are giving 1 so you never know so in this place you have to apply 4 tristate buffers so on every end gate you will apply a tristate buffer so the end gate output you are interested in that tristate buffer will be activated the output of that tristate buffer will be given on a common point the other 3 end gates will be deactivated with the help of the output buffer of the tristate buffer you deactivate the output that is the control pin you connect it on a logic low so that means the output is disconnected now what you can do basically the output pin can be used as an input so if you apply a variable it will be available the 1 to 2 multiplexer on one input by setting the select input s1 to 1 input 1 will be selected that output will be available and that output you can apply on the input of the end gate we have seen the circuit diagram GL22V10 PLT device we have seen the circuit the inputs and outputs the all max then we have seen the other circuit the detail circuit diagram of all max if you remember in the beginning GL22V10 device there are 10 all max on every all max there are different number of product terms basically 10, 12, 14, 16 and 8 these are the product terms let's see the detail the connection of all max there are 8 product terms with the end gate array the end gate array has 8 product terms so let's see the connection and after that let's see how to program it the output of all max basically it is going to give you sum of product terms so sum of product terms how many product terms can come basically if you think 8 product terms can come because 8 inputs are connected on the gate and 8 inputs are coming from the end gate array similarly if you see the other all max 10 product terms are coming from the end gate array so the output of all max and how many product terms can come so all together if you see this device how many product terms can generate basically 10 all max and 10 outputs so 10 separate sum of product functions can be implemented so let's see the detail connection of the first all max with the end gate array let's have a look at the detail circuit diagram of the first all max the end gate array in this you can see the set of vertical lines and horizontal lines the vertical lines are in 4 groups you can see 11 groups so these 11 groups of vertical lines are representing input lines basically you can apply input variables if you see below you can see the pin which is connected to an input buffer so the input buffer the variable applied the uncomplimented form is connecting from the first 2 vertical lines if you see in this group 2 inputs are coming from all max circuit as I told you the output pin can be configured as an input pin so the variable applied can be connected to an input pin as you can see the first 2 vertical lines are connected to an input the next 2 vertical lines are connected to an output pin which you can configure as an input pin the next set of 4 vertical lines is connected to an input pin that means you can apply another variable the third, fourth, fifth, sixth you can connect different input variables so these vertical lines are representing different variables or inputs the horizontal lines are showing that they are 44 horizontal lines or 44 inputs to each AND gate how these 44 inputs are basically G, A, L, 22, V, 10 there are 12 inputs and 10 outputs so basically 22 inputs can be each input has an uncomplimented output or complemented output so basically each input has 2 outputs since there are 22 inputs you have 44 lines so as you can see each AND gate input has 44 input lines these horizontal lines are representing product term lines now if you have to implement any product term you will connect the horizontal line with a vertical line how will you do that basically each cell is a cell on each intersection E square CMOS cell so in this diagram there are many E square CMOS cells which are not shown here if you look at AND gate outputs these AND gate outputs are not connected in all mac so the first AND gate is used to reset and these are connected with all the other AND gates the second AND gate is used to control the tri-state buffer so if the second AND gate is high the tri-state buffer will be activated and information will come if the second AND gate output is low or zero tri-state buffer will be disabled and open circuit that means the output pin will be configured as an input the other AND gates the product terms are connected with all mac input as we saw earlier in this all mac there is an OR gate with which these AND gate outputs are connected let us see how we can program this particular output if you look at the first group you can see some fuses so these fuses indicate that these product terms are activated similarly in the second group in the third group in the fourth, fifth and sixth group you can see some fuses that the output sum of product form expression of all mac 1 we are using 6 literals we are using 6 variables so we can call them A, B, C, D, E and F in this now the first AND gate which is connected with all mac you can see that 6 terms are connected so let us say A, B, C, D, E and F are connected the second AND gate with which the literals are connected A, B, C, D, E, F similarly the third AND gate with which the terms are connected A, B, C, D, E, F similarly the fourth AND gate with which the inputs are coming A, B, C, D, E and F the last three AND gates the inputs are coming A, B, C, D, E, F the second AND gate with which the input terms are coming A, B, C, D, E, F and the last AND gate with which the input terms are coming A, B, C, D, E, F the output of all mac we will get through the output of OR gate now OR gate now OR gate will give some product expression that expression will be based on these six product terms which we have discussed the last group of four vertical lines you can see a fuse and tech basically you have activated the tri-state buffer so the control line is high the output of the OR gate is available at the output pin we saw the circuit diagram of GAL we saw the detail circuit diagram discussion will continue on these circuits in the next lecture we will meet again take care of yourself goodbye