 Hello and welcome to this presentation of the STM32F7 system configuration controller. STM32F7 microcontrollers feature a set of configuration registers. The system configuration controller gives access to the following features. Remapping memory areas. Managing the external interrupt line connection to the GPIOs. Certain robustness features. Selecting Ethernet PHY interface. And finally the configuration of the 20 milliamp high drive IOs used for I2C fast mode plus. Certain features such as flash bank swap, dual boot, and class B system configuration register are not available on all STM32F7 microcontrollers. Please refer to the respective reference manuals. The SWP FB bit in the system configuration remap register allows swapping of flash memory banks 1 and 2 which allows booting either to bank 1 or bank 2. The memboot bit in the same register allows software to identify the boot address and in conjunction with boot add-ex option bytes it allows identification of the boot schema and the running firmware. For STM32F7 microcontrollers with the dual bank flash feature the FB mode bit determines the address mapping of banks 1 and 2. The SWP FMC bit in the system configuration remap register allows remapping the FMC controller's SD RAM banks 1 and 2 to the NOR RAM bank base address which allows changing the SD RAM memory's attributes. When FMC bank swap is enabled the NOR RAM bank is remap to the SD RAM bank 1 address. The class B system configuration register contains the control and status bits linked to safety and robustness. Two control bits direct certain error detection events to the timer's break inputs. This allows timer outputs to be placed in a known state during an application crash. Once programmed the connection is locked until the next system reset. These internal events are the power voltage detector event and the Cortex M7 lockup state. The system configuration controller manages the selection of the GPIO to the external interrupt or event signal which is used as asynchronous external interrupt or event with wake up from stop capability. It also contains the I2C IOS fast mode plus 20 milliamp drive enable control bits. Four IOS can be configured in high drive mode even if they are not used as I2C alternate functions. They can be used to drive LEDs for instance. The values on the boot pin are latched on the fourth rising edge of the SYS CLK signal after a reset. It is up to the user to set the boot pin after a reset to select the required boot mode. The boot pin is also resampled when the device exits standby mode. Consequently they must be kept in the required boot mode configuration when the device is in standby mode. After the startup delay the boot space is selected before releasing the processor reset. The boot ADD0 and boot ADD1 address option bytes are used to program any boot memory address from 0x0000000 to 0x3FFFF which includes all flash address space mapped on the ITCM or AXIM interface. All RAM address space, ITCM, DTCM RAMs and SRAMs mapped on the AXIM interface. And the system memory boot loader. The boot ADD0 boot ADD1 option bytes can be modified after a reset in order to boot from any other boot address after the next reset. If the programmed boot memory address is out of the memory mapped area or in a reserved area the default boot fetch address is programmed as follows. Boot address 0, ITCM flash at 0x000000 Boot address 1, ITCM RAM at 0x0000000 When flash level 2 protection is enabled only a boot from flash on ITCM or the AXIM interface or the system boot loader will be available. If the already programmed boot address in the boot ADD0 and or boot ADD1 option bytes is out of the memory range or RAM address on ITCM or AXIM the default fetch will be forced from the flash on the ITCM interface at address 0x0000000 When dual boot mode is enabled the boot is forced to the system memory. The system memory firmware will boot firmware in bank 2 if it is valid otherwise it will boot in bank 1. For more details on dual boot please refer to application note AN2606. Boot ADD0 and boot ADD1 address option bytes allows programming of any boot memory address from 0x0000000 to 0x2007FFFF including all flash address space mapped on ITCM or AXIM interface all RAM address space ITCM, DTCM RAM, SRAM1 and SRAM2 and the system memory boot loader. The boot ADD0 boot ADD1 option bytes can be modified after reset in order to boot from any other boot address after the next reset. If the programmed boot memory address is out of the memory mapped area or reserved area the default boot fetch address is boot ADD0 ITCM flash at 0x0000000 and boot ADD1 ITCM RAM at 0x0000000 When the dual boot condition is respected the STM32 boots from the system memory if the expected boot address is defined within the main flash address. The STM32F7 boots from RAM if the boot address is defined in RAM. If none of the previous conditions is valid the boot is forced to the default memory location. Dual boot mode is supported even when the STM32F7 is protected with readout protection level 2. When STM32F7 readout protection level 2 is enabled the boot address is restricted to only addresses in flash. When in single bank configuration any programmed boot address out of the memory range or RAM or system memory address the default fetch will be forced from flash on the ITCM interface at address 0x0000000 In dual bank configuration the STM32F7 boots in flash bank 2 if it is valid, otherwise in bank 1. The on-chip bootloader allows the user to program the flash memory through a serial communications peripheral. The supported protocols are USART, USB, CAN, SPI and I2C. Note, the DFU CAN may work with different values of the external quartz oscillator in the range of 4 to 26 MHz and the USART uses the internal HIS. In addition to this training you can refer to the reset and clock control, power controller, interrupts, flash and system memory protections, timers and I2C trainings. For more details please refer to application note AN2606 STM32 microcontroller system memory boot mode.