 Hello, and welcome to this presentation of the STM32 Quad SPI memory interface. It covers the main features of this interface, which is widely used for connecting external memories to the microcontroller. The Quad SPI memory interface integrated inside STM32 products provides a communication interface, allowing the microcontroller to communicate with external SPI and Quad SPI memories. This interface is fully configurable, allowing easy connection of any existing serial memories available today on the market. Applications can benefit from the easy connection of external serial memories, requiring only a few pins. Thanks to the memory mapping feature, external memories can be simply accommodated in the existing project whenever more memory space is needed. The Quad SPI memory interface integrated inside STM32 products offers three operating modes and is optimized for communication with external memories with support for both single and dual data rate operation, allowing the access of 8 bits in single read cycle in DDR mode. When the Cortex-M4 frequency is below 50 MHz, the Quad SPI block can use the same clock frequency for the bus. When the Cortex-M4 frequency is higher, up to 64 MHz, the Quad SPI prescaler must ensure a clock division by at least two. The Quad SPI memory interface operates in three modes, one, in direct mode, where it behaves as a classical SPI interface, and all operations are performed through registers. Two, status polling mode, where the flash status registers are read periodically with interrupt generation. And three, memory mapped mode, where the external memory is seen as an internal memory for read operations. The Quad SPI memory interface offers high flexibility in frame format configuration. This flexibility allows addressing of any serial flash memory. Users can enable or disable each of the five phases and configure the length of each phase as well as the number of lines used for each phase. The Quad SPI memory interface used in indirect operating mode behaves like a classical SPI interface. Transferred data goes through the data register with FIFO. Data exchanges are driven by software or by DMA, using related interrupt flags in the Quad SPI status registers. Each command is launched by writing the instruction, address, or data depending on the instruction context. A specific mode has been implemented in the Quad SPI interface to autonomously pull the status registers in the external flash memory. The Quad SPI interface can also be configured to periodically read a register in the external flash memory. The returned data can be masked to select the bits to be evaluated. The selected bits are compared with their required values stored in the match register. The result of the comparison can be treated in two ways. In ended mode, if all the selected bits are matching, an interrupt is generated. In Ord mode, if one of the selected bits is matching, an interrupt is generated. When a match occurs, the Quad SPI interface can stop automatically. The Quad SPI memory interface also has a memory mapped mode. The main application benefit introduced by this mode is the simple integration of an external memory extension, thanks to there being no difference between the read accesses of internal or externally connected memories except for the number of wait states. This mode is only suitable for read operations and the external flash memory is seen as an internal one with wait states included to compensate for the lower speed of the external memory. The maximum size supported by this mode is limited to 256 megabytes. The pre-fetch buffer supports execution in place, therefore code can be executed directly from the external memory without having to download it into the internal RAM. This mode also supports SIOO mode, or send instruction only once supported by certain flash memories, which allows the controller to send an instruction only once and to remove the instruction phase for following accesses. Read data sampling allows users to compensate for the delay of signals due to constraints on the PCB layout optimization. It allows applications to shift the data sampling time by an additional one-half clock cycle when operating in SDR mode. In DDR mode, the output data can be shifted by one-half system clock cycle to relax hold constraints. The Quad SPI memory interface has five interrupt sources. Timeout, status match, when the mask received data matches the corresponding bits in the match register in automatic polling mode, FIFO threshold, transfer complete, and transfer error. DMA requests can be generated in indirect mode when the FIFO threshold is reached. The Quad SPI memory interface is active in run, sleep, low power run and low power sleep module. A Quad SPI interrupt can cause the device to exit sleep or low power sleep modes. In stop zero, stop one or stop two mode, the Quad SPI is frozen and its register's content is kept. In standby or shutdown mode, the Quad SPI is powered down and it must be re-initialized afterwards. Wearable applications require low power management functions together with sensor data logging and possible audio interface. This can be achieved using the Quad SPI interface to store in an external flash memory data log for sensor. Additional audio data for ringtones or audio message generation can also benefit from the large space offered by an external flash memory. The low pin count needed to drive such devices allows for a highly optimized system integration. You can refer to the peripherals training slide related to RCC, interrupts, DMA and GPIO for additional information. For more details, please refer to the following documentation available on our website.