 So, welcome to this lecture on advanced digital system design in the course digital system design with PLDs and FPGAs. The last lecture we have started with the effect of metastability in sequential circuit and data path. We did not spend much time on how the metastability happens in a flip flop or latch or anything like that though briefly I mentioned the cause of it in a just essentially our focus was to look at the effect of metastability in sequential circuit and data path and how to handle that situation. So that the proper operation of the circuit is not imbibed definitely analysing the metastability in detail starting with the cross coupled latch moving to kind of edge to get flip flop and now we will bring clarity. But due to lack of time we will set that aside and focus on the what is useful for the design of the digital system we will handle it that is a plan. So let us run through the slides we have looked at the last lecture. So we know that in an edge to get flip flop for the data to appear at the output from the input the input data has to satisfy some timing requirement with respect to the clock edge active clock edge. The data has to arrive sometime before that is called setup time not only that it has to remain at the input after the clock edge for a while that time is called the duration is called whole time if that happens then from the clock edge with a delay the output appears ok. And this I said if you analyse a master slave flip flop which from which this edge to get flip flop is constructed during the negative for a positive edge to get flip flop during the negative clock period the master is in transparent mode. So the setup time would normally mean from the active clock edge that is from when the master is going to be cut off from the input that actually the maximum minimum time required for that latch to set because that is when the latest the input can change if afterwards the input changes there is not enough time to set the master latch. So that is what is the setup time of course normally in the clock path there will be inverters to choose the correct polarity and to choose the opposite edge for the slave and all that. So normally there will be 2 inverters so that inverters queue has to be removed from the setup and the whole time is that inverter delay itself because even after the clock going high it take that inverter delay for the master to cut off that is a hold. So during that time the data should not change and when the positive clock edge comes the slave get the copy of the master slave is enabled the master is disabled. So for the time for slave to set as a propagation delay normally again there will be an inverter that delay has to be added with the latch delay slave latch delay for the propagation delay. So that is a essence of this setup hold and propagation delay but again in a basic course many a times you are told that if this is met the input is captured at the output kind of truthfully but many a times it is not discussed what happens if it is violated ok. So many things can happen as we said if the setup and hold time is violated kind of the flip flop can miss trigger that means suppose the previous value was 0 and was trying to set to 1 it may remain in 0 or it may kind of set to 1 ok. Now so it means that you are not really sure what the output is going to be it could be 0 or 1 but as I said normally it is not a dangerous situation as long as input persists for at least 2 clock periods then definitely in the next clock edge everything will be ok because it will meet the setup and hold time and then the data is captured at the output properly ok. So miss triggering itself is not a very serious issue but the second effect is that it might take longer time to resolve it that means if the data changes close to the active clock edge it will take long time for it to settle and that is dangerous because like we have in a sequential circuit we find the minimum clock period. And once you decide that if the data the output takes longer to settle then it can violate the setup and hold time at the destination register no issue with this flip flop but it is driving something at that destination register it can upset the setup hold time. And the worst effect would be that this output can get stuck to a voltage level which is not neither 1 nor 0 it will be in between and that can drive the any circuit not even flip flop it can even drive the combinational circuit into active region the gate and that will act as amplifier any slight noise it will start switching it will dissipate lot of power may be it is taken care in the design depending on how you design. But definitely this is quite disastrous that it gets stuck in between and the worst thing is that we cannot definitely say when it will come out of it we can only say about the probability so that means it can remain there for a long time when we talk about probability that does not kind of preclude chances of it getting stuck for a say 5 second or 5 minutes or anything like that though we talk about the probability you should remember that but that happening often when the probability is low may not happen but then like the probability is probability so you should not have kind of a deterministic view on the probabilistic events that should be kept in mind. So let us come to that the effect of it but in a sequential circuit or in a data path we take care of all these we like we choose the proper clock period to meet the setup time we analyse the effect of this Q we analyse the effect of whole time and this Q effect on both we will consider though we have not discussed that in the in our lectures but we will be doing that when I take the FPGA part of the course. So in a data path we do the maximum frequency analysis whole time violation similarly in a FSM we do both and then when the metastasphalic can happen in this circuit is a question we said yes there could be inputs directly coming to this combinational circuit in a data path there could be inputs coming to the first stage of the data path may be this continues you know there is registers combinational circuit registers combinational circuit and so on. But at some point somewhere some data from the external world or the data path comes in and in an FSM there are inputs mainly this is from the data path. But we are not sure the frequency of the clock from where this input is coming ok may not be same so or it could be a some process which is generating a logic value like a limit switch which is now relation with the clock many a times and then these inputs may not meet the setup and whole time as far as this input is concerned may not meet the setup and whole time and as far as this is concerned it may not meet the setup and whole time. This latency as I said is a matter of shifting it does not affect the probability of any particular input you know getting creating metastability in this flip flop. So the problem as far as a sequential circuit or a data path is concerned the asynchronous input is the one which can cause metastability. So once again though we have learned metastability our concentration as far as sequential circuit and data path is concerned should be on inputs which are not synchronous ok. So if you are a good designer that there you should focus your attention the inputs coming from an asynchronous domain ok that should be handled properly that is where the crux of the problem ok that is like asynchronous input. So when we say asynchronous input will be an input which is generated as a on a flip flop or a register with a different clock or a process which is not synchronized to the sequential circuit. So very easy to answer this question that the problem is that the input is asynchronous. So the solution is to synchronize it and it is again we do not know probably at the beginning you do not know how to synchronize but it is very easy. Suppose there was an asynchronous input which was going to this combinational circuit and reaching a destination register. The way to synchronize is that you connect that input asynchronous input to a D flip flop clock by the same clock as a sequential circuit and the queue is connected here. Now what happens is that the D is captured by this and appears with a delay. Now any time D changes this is captured at the queue with a delay of propagation delay TCO and that you know transmit through the propagate through the combinational circuit reach here. So if the clock period is chosen properly in the next positive edge here this input that means the output of this synchronizing flip flop will meet the setup time and whole time there should not be a problem. And of course the input which is synchronized will reach at this destination register with a latency or a delay of one clock period. So that is a penalty we pay, penalty in terms of time that there is a latency and penalty in terms of the area which is a flip flop ok. So nothing comes free. So you suffer in delay and suffer in the area ok that you should know. Now as I said we have not solved the problem in a very kind of foolproof way earlier there were chances of all these or some of these flip flops getting into metastability. Now there is no guarantee that this will meet the setup and whole time of this flip flop because this is asynchronous with respect to this clock. So this can get into metastability ok now that is better than the earlier case but like we are kind of sampling the asynchronous input in one point but earlier it was sampled by different flip flops and maybe some will get into metastability some will not, some will miss trigger it was a mess ok it was you could not say what is a kind of what is happening at the output you know some could be 1, some could be 0, some could be in metastability and so on ok. Though the way I say you might think that it occurs so frequently it does not ok but you know that I want to highlight the problem of sampling an asynchronous input at multiple places with different path delay ok that is the issue. But our hope is that if this synchronising flip flop get into metastability by the next clock edge if it comes out of it and if there is enough time for it to propagate through combinational circuit and meet the setup time at the destination register it is ok ok. So that is the real hope but like this I want to state I can only kind of make a statement we are not going to analytical part of it. The fact is that the probability of a flip flop remaining in metastability decreases exponentially with time that means if this synchronising flip flop get into metastability as the time passes the chances of it coming out becoming exponentially more. So every nanosecond you give extra it is an exponential increase in the probability of it coming out of the metastability again I want you it is a probability I mean it is not certain like you cannot say after you give one nanosecond extra it is surely now with a double chance it is going to come out it may remain there ok there is a kind of logical problem in the last sentence but like I hope you got the picture. So the idea is that we give enough time for the synchronising flip flop to come out of the metastability in which from now onwards we can analyse that part the time available for it to come out of metastability is that in this part there is a clock period one clock period a clock comes and before the next clock edge this output should reach here but now if it get into metastability it should come out propagate and meet the setup time here ok. So how much time is available for it to come out of metastability that is the total clock period minus this time for the propagating through the combinational circuit minus the setup time at least by then it should come out ok suppose the clock period is 10 nanosecond setup time is 1 nanosecond and the combinational delay is 4 nanosecond. So put together it is 5 nanosecond so we are hoping that within 5 nanosecond after getting into metastability this comes out of it then there is no issue everything goes clean but that also tells us that if you are able to give more time like then there are more chances of it coming out of metastability. So it is a question of analysing it finding the probability and checking is that ok not only the probability maybe we have to convert that into the rate of metastable kind of failure metastability failure in the sense that it does not come out of metastability or the average time between such failures ok. So if it is large enough and if it occurs very seldom then it is ok ok. So but if that is not ok like you have the metastability resolution time for a single stage is t clock minus t com minus t setup then we have to increase it we cannot kind of at least from the outside we should not tamper with the clock period if you reduce it the system will suffer so we reduce this combinational circuit and we are trying to make it 0 and that is by you know that by putting another register in a chain here so that the output of this flip flop see only a flip flop not a combinational circuit. So that is double stage synchroniser so we put 2 flip flop now the time available for this to come out of metastability is clock period minus a setup time ok. But the price we pay is a 2 latency 2 clock period latency so if something happens here the worst case it will appear here after 2 clock period ok that is and of course in terms of area 2 kind of flip flops. Now suppose like you know kind of assess the probability and find that it is not enough the mean time between failure is not very large then we will be forced to kind of increase the clock period. But then this should not be affected so what we do is that we divide the clock for this part and retain the original clock for this sequential circuit or the data path mean data path. So that is what is shown here so you divide by n the clock is coming from here the main clock goes to the sequential circuit divided clock goes to the synchroniser and now we have the clock period is n into t clock because we are dividing by n then the clock period increases by n minus setup time so that should normally solve the problem n is and now the latency is 2 clock period of the divided clock which is n t clock. So 2 n t clock is a latency which can be high but n itself is 2, 3 or 4 things like that not a huge number but I said there is an issue here of a skew because there is a skew between this clock and this clock this source registers clock is a delayed version of the destination register clock. So like if you put the destination clock like that and the source clock is coming delayed okay so that it into the available clock period so available clock period for the propagation will be t clock minus this skew. So this skew will force 1 to increase the clock period okay that is not a good idea and we will definitely analyse the effect of skew in the clock period all that in the whole time violation and all that in different scenarios you know there could be different scenario depending on where which side the clock comes from. So we will analyse all that but at least I want to tell you the problem here so what we do is that to avoid that we put a d skew flip flop because now the skew come between 2 adjacent flip flop without any combinational circuit so it is kind of you know t clock minus skew should accommodate the tcq and the t setup which will be much smaller than this will be much smaller than this which is like this suppose if there is a skew here the situation is going to eat into the clock period and it is going to push the clock period up okay. So this would end and that is the d skew flip flop definitely it will add latency to the whole process now so it will be the latency you can work out it is a 2n t clock plus the t clock because this is not clocked by this kind of output of the counter but the input of the counter. So that is what we have looked at the last class I have repeated it because it is important that should get into your mind very clearly and this is a kind of standard solution almost people treat it as a kind of thumb rule wherever they see in a synchronous input they put 2 flip flop in a chain sometime they put 3 flip flop okay we will see why 3 flip flop. I do not quite agree with such kind of thumb rule like which is like many a times if you ask some people like you are sampling an input say the nico straight how many times you should sample they will say 10 this 10 is not a magical number you know that we have 10 fingers in the hand so we and we use a decimal system maybe because we have the 10 fingers in the hand because earlier the counting was you know based on the fingers and we will keep a tally for how many 10s and that is how the decimal system you know kind of arrows and before that people were like even for now for the time we use tall as a base. So there were like do decimal number system are there so what I am talking is that my argument is that if we add tall fingers then we will be all the time telling tall rounding off to tall everything. So just relying on thumb rule for design is a very bad thing and nowadays anyway it does not work because people want very optimized circuits in terms of area power dissipation delay and so on. But you should as a designer you should not resort to these kind of the magical tricks which is told by other people to do that where whenever you see an asynchronous input two flip flops or three flip flops without any questions ask not a good idea at least when you are working in a CMOS technology you know the kind of the delays you can expect in that technology and from there you go back and analyze it is the data is difficult to come by for metastability analysis. But I am hoping that you can get it at least look at some the published work on that and you know assure yourself that the scheme you put is enough or it is not kind of you cannot over designing and so on like where you the two double stages enough do not put multiple stage cycle multiple cycle synchronizer and so on. So let us come back to it instead of multiple cycle synchronizer sometime people put a kind of cascade at synchronize that means they will put three flip flop in a chain four flip flop in a chain and so on. The argument is that like say you can work out the probability like if you know the frequency of the clock and the setup and hold time window width and if you know the rate of change of the asynchronous input because this need not be kind of regular square wave. So the average rate or the maximum rate whatever depending on average rate should be good enough to take and then you can find out the rate of metastability entry then knowing the time that the fact that it will as you give more time the probability of it coming out increases exponentially with time. So the probability of it remaining there decreases exponentially with time okay. So from there we can find out what is the rate at which the second flip flop can get into metastability. And again do the same analysis for the second flip flop then you know what is the rate at which the third is kind of getting. But so this you know that the probability gets multiplied and the chances are becoming less and less for you know when you come towards the real sequential circuit the probability of that the last flip flop getting into metastabilities very very very less. So the mean time between failure will be a huge numbers in terms of maybe millions of years that should be good enough for large number of products which you make out of that design okay. So that is the basic idea about the cascaded synchronizer. The probability of metastable output reduces multiplicately that means that remaining in metastability reduces at each stage of the cascaded synchronizer. So some people do this instead of and it does not matter you know to be very frank like here like if you assume 4 flip flops okay. So you have a latency of 4 here okay. And you are using kind of 4 flip flops. And if you go back to this and you put a divide by 4 counter mode 4 counter then use 2 flip flop the latency is 2 and t clock which is nothing but the 4 clock cycle of this. So essentially kind of things are you know similar there is no difference it is a matter of kind of some choice only thing is that maybe this introduces as Q but in the cascaded there is no Q. So many times when you see some kind of solutions at least theoretically sometime it all means the same though the argument the structure is different. So one should look at it and try to make sense out of it okay. Now let us look at the effect of asynchronous input to FSM. Now I must warn you saying that there is no reason for you not to synchronize an asynchronous input in a very serious design maybe this concern is little bit old where one use to use kind of discrete kind of devices where a flip flop can be very costly maybe putting 2 flip flop will end up you will end up using a kind of 20 pin or 24 pin dip package which occupies. But nowadays the SOC chips are you know it is so small and there are so much density of transistors or gates not a problem not much of a problem but then it is nice to analyse at least academically we learn something in a complex situation what is the effect of the asynchronous input that is the only thing. So I would suggest that if there is an asynchronous input synchronize it rather than applying these techniques which I am going to say. So assume that this enable is an asynchronous input to a state machine and the state machine is like that as long as it is low remain there if it is high transit to the state with 11. Now mind you there are 2 flip flops Q1 and Q0 and now the situation is that we are not synchronizing this asynchronous input is going to the input of Q1 that flip flop and the 0th flip flop ok. Now because of the path delays difference in path delays this will be sampled at different point in time and you can imagine some time may it may happen that the Q1 transit to 1 and Q0 remain there because it is asynchronous or the opposite can happen the Q1 remain in 0 that means mistriggered it retain the previous value. But the Q0 as transit so it may happen that instead of the valid state 11 when the clock comes it transit to an kind of invalid you know state 10 or 01 and we do not know about the state and this could be kind of you know some state within the state diagram or it could be a new state whatever it is dangerous this is not like output races where it goes briefly there and come back it really mistriggers so you can imagine that you have a very complex state machine which loops and branch and all that suddenly you find that it is in some state and soon you find that the state machine is elsewhere and it continues from there and it is quite dangerous so you should never suppose if you are not synchronising the solution is not to do such a kind of assignment you should make it gray code so that only one of the flip flop change so even if there is a mistrigger it does not matter either it will remain 00 or it will transit to 01 so always do a go or no go like enable bar remain there enable go there but this should be gray coded if you are using an asynchronous input the similar situation can happen when the state machine is in say 00 and enable is an asynchronous input when it is 1 you transit to 01 when it is 0 the machine transit to 10 okay the state machine transit to 10 now since once again since it is we are talking about in this condition when enable is 1 q0 is changing the state when enable is 0 q1 is changing the state now you can imagine that this two flip flops sibling the one input with different path delay so it may happen that one instead of both changing one might change so you are end up you are hoping like like here sorry here only the q1 was changing here only the q0 was changing but q1 will kind of interpret it as 1 and will change and q0 also will interpret it as 1 and change then you will end up in another invalid state alright and this is quite dangerous again the solution is that never branch on asynchronous input like this like when it is 1 go to some state and 0 goes to other state you should always adopt a go no go structure when it is 1 transit when it is 0 remain there and this should be gray coded and as I said always it is even better to synchronize the asynchronous input without much botheration unless it is a very small circuit you are trying to suppose you are making a 4 bit counter and you have an up down input direction input from somewhere and if you double synchronize up down and direction then that will end up using for flip flop which is equal to the counter flip flop so but these situations are rare and if at all use a 4 bit counter it will be a very small application so that you should kind of remember so better to synchronize the synchronous input the related to it so now essentially what we have covered is the how to handle what is meta stability what is its effect on a flip flop and in a sequential circuit and data path how it affects and how to I mean where the problem really come in a sequential circuit or in a data path and we said the problem is asynchronous input the solution is to synchronize it so we have looked at the single stage synchronizer double stage synchronizer which improves the reliability or the probability aspect is improved then multiple cycle synchronizer or cascade synchronizer and we have seen what happens if you use a synchronous input in an FSM to make branching okay so we have seen one branching with multiple flip flops changing at the same time and one branching where depending on that input it make a decision to go to one side or the other side so that is what we have seen. Now a related kind of scenario is just something called reset recovery time okay and that is related to the asynchronous reset in a flip flop which is kind of this recovery time the notation is trc like t rec is a recovery time or trr okay the rr and rec is the subscript. So essentially this unit of kind of realized or learned and nevertheless it is a very very important aspect you would have assumed that at least the behavior of an asynchronous reset in a flip flop is that you assert that you make it active with a delay the queue goes to 0 and you remove it then the clock comes everything works fine is what we assumed okay. But there is a factor called recovery time that means that the reset recovery time is a minimum amount of time between the de assertion of this signal and the next clock edge active clock edge suppose the clock is coming the positive clock edge is coming here the research should be removed sometime before that okay otherwise this output can get in the metastability okay and this is quite serious because in a digital circuit there could be tens of thousands of flip flops okay or hundreds of thousands of flip flops and many a times at the power on a single reset we can reset all the flip flops okay most of the flip flop and it has to be reset because precisely same reason there is no guarantee that if you power on all the flip flops all the outputs are going to be neat you know like during the power on probably it can get into metastability. So reset is essential but if you do not meet the reset recovery time in flip flop again the metastability can happen in the flip flop so this is something which is overlooked and many a times one think of the assertion of the reset not the de assertion that is a problem like we are not asking the right question when you assert it fine the reset is driving the internal latches you know that is the problem like in an edge to get flip flop you have a master latch and a slave latch as I said that is and this reset asynchronous reset is directly going to the master latch and slave latch and resetting it and you can look at the circuit diagram for it then you will realize why that happens okay. Then in this course I do not have time to go into the details of that because it will eat up into our time so when that means they are driving the master and slave latch directly not going through this clock gating you know that is why it is asynchronous as soon as you assert with a delay this is reset the output is reset the clock does not matter because it is going directly into the latch and what the clock does is that it gates the input to the master latch so on. So we are bypassing that but now when you remove it may happen that you are kind of this is being input is driving the master latch and it is nearing that setup time it is close to that minimum time required for it to setup and you are messing it with through the reset it is trying to set through the D and we are removing it we have driven into 0 but we are removing it very close to the clock end so then this will not have enough time to set it up. So this should be and how much time is not the setup time because this is directly going to the latch so this is the kind of reset recovery is the time delay of that path where this reset is going and kind of resetting the latch okay that path like if you analyse the detailed circuit you can find a reset recovery time in terms of the gates involved and so on okay. But I hope you get a picture of the situation okay that is a problem like you can assert it any time with the delay it will be a kind of reset because it directly going it does not matter but when you remove it and it is near the positive clock end near the setup time then this thing can get into metastability because 2 drives are there and this does not have enough time to drive it to the proper value so this can get into metastability. So this has to be met and that is now so you would see that most people most vendors or designers would advise you to use synchronous reset because it is safe okay. But there is an like nice feeling about asynchronous reset saying that like the outputs the flip flops are reset without a 1 clock period delay because in the case of synchronous reset there could be a the worst case 1 clock period delay for it to reset okay. So if you want to reset something very quickly even before that for whatever reason maybe for kind of reliability fault tolerance or critical situation whatever this may be good. So now I know understanding the reset recovery what is the solution okay now if you say kind of okay let us synchronize a synchronous reset then it is like synchronous reset only because what synchronous reset do we do it outside it really it meets this kind of reset recovery time but then it is a synchronous reset the behaviour is synchronous because you assert the reset it comes with the 1 clock period delay or worst case 1 clock period delay it is like the synchronous reset. But we can say this with certainty so let us not synchronize the leading edge but let us synchronize the trailing edge because if you do not synchronize the leading edge as soon as you assert it the reset happens and the problem is about removing it near to the clock edge. So if you synchronize to the clock edge it is removed after the clock edge and it will definitely meet the recovery time at the next clock edge so that is the idea. So that is what I have written here to retain the asynchronous reset behaviour only the trailing edge of the asynchronous reset should be synchronized so that is the game. So I am showing straight away a possible kind of solution there are many other but I am showing again the simplest one so assume there is a power on reset circuitry which has no kind of relation to the clock it comes so if it is kind of going to the asynchronous reset of the flop then it can cause metastability so we are synchronizing it. So this is the synchronized version of the reset it is an active high reset signal as the name suggests it is active high and you can imagine that this part is a delayed the worst case 2 clock period delayed version. So now the trailing edge comes much later now what we are doing is that we are oaring together okay so what happens is that the leading edge come as it is because it is oared with the delayed version but the trailing edge is synchronized version. So that is the clever trick for a active high reset now the same technique I hope you got this we have a double stage synchronizer for the power on reset. So this is a synchronized version but both the leading and trailing edge are not synchronized now what we do is that we kind of oared the original reset so that we get the leading edge as it is okay. So it is kind of oaring of a pulse with the delayed version of the pulse so you get the leading edge as it is and the trailing edge is a synchronized version which comes with a late kind of worst case latency of 2 clock period okay. Now for the active low signal that means this is kind of like it goes in the opposite direction it is 1 then it goes 0 and come back to 1 so we do we replace this AND or gate with an AND gate then we have done it okay. So it is a kind of 0 and a delayed version of 0 you know that for the AND gate any input is 0 the output is 0 so it is like as far as active low signal is concerned we have studied at the beginning if you remember we have looked at the difference between AND function and AND gate okay. Now this is an AND gate doing an OR function for an active low signal so for an AND gate the inputs and outputs are active low then it is doing an OR function and we have discussed this in the overview when we have kind of done a review of the basics we have done that and that is basically I have told at that point in time that is bringing in the De Morgan theorem into our concept okay. So this is the circuit for active low reset and naturally when in a chip there are lot of flip flops to be kind of reset so it is not a good idea that one wire you know drive everything you know you need to kind of buffer it properly for the because the fan out is limited if suppose the fan out of a gate is kind of say 50 then if there are 1000 then you need 20 buffers and now you have to balance it out it is not a good idea that you put a buffer then you drive 20 then again you buffer it so everything get delayed in a chain so you do a balance buffering and this goes to however money you want you put it parallely and these branches dry out sub sections of the circuit okay that is what is shown here. So essentially what we have looked at in the last few slides are the reset recovery time which is related to the metastability this is related to the asynchronous reset of a flip flop since the asynchronous reset is kind of driving the internal latches directly if there is no problem in driving it but while removing it if the clock edge is kind of is near to the clock edge then that is the set up path set up time of the input that can kind of interact with this drive and cause metastability in the output of that flip flop. So the solution is to synchronize but then it does not have an asynchronous behavior so again we said it is fine if you synchronize the trailing edge rather than leading edge and the solution we have looked at is that let us synchronize it but do an OR function okay. So in the case of an active high reset we use an OR gate and for an active low reset we use an AND gate and that was the solution. So kind of I wind this metastability synchronization part here so the essence is that when you find an asynchronous input you have some idea of what is the mean time between the failure with regard to the metastability or when there is when you encounter the asynchronous input and do the synchronization and we have not handled all possible ways of doing synchronization but this is by far the most useful part at least for a basic course I think that should be good enough and of course the reset recovery again we have discussed what to do which but this has to be applied kind of without any hesitation whatsoever okay. So that you can blindly kind of replicate whatever I have told. So let us move on so with this I have kind of I am winding up the digital design part of my course I have given you how to do a hierarchical top down design we have seen an example of a CPU then we have looked at what is data path what is controller what is a controller behavior what is a structure how to design that structure how to design a control algorithm whole methodology we have seen and we have looked at a case study where everything is applied all these principles are applied very maybe not a very complex case study but it was a kind of real life case study we have looked at all the practical steps then we have looked at the various issues in the finite state machine like power on reset clock frequency output races then we have looked at the problem of state assignment unused states then we have looked at how to reduce output delay by decoding from next state logic by encoding the output in the state bits all that and then we also have come to this problem of metastability in flip flop asynchronous input synchronizing it reset recovery so kind of I have covered and I have given a kind of a review of your basic you know basics you have learned in the undergraduate course so that you are familiar. So I think with this you should be able to kind of make a good design and we will take case study now we have learned VHDL we are kind of completing that and now what is remaining is the two devices device technologies the programmable logic devices and the field programmable gate array ok. Now once I complete that and bit of VHDL we have not covered the test bench then we can kind of look at the case studies where we play with the tool we implement that on a board I do not have too much time to show you lot of case studies and so on but then I will show something that should be enough and nowadays the people are kind of solving lot of problems you know like say in mathematics the people try to solve all kinds of problems and yes that is good because that makes you kick and that works out in examinations where in a short period of time you are able to solve more number of problems but in real life many a times that is not the situation that is not that in a fraction of a second you have to solve a problem ok. You have to solve a problem creatively elegantly without much cause without causing harm to the humans environment and things like that ok and so if when you work out some example case study that should have the real life element in it it should address all the basic issues involved so that then very few case studies are enough instead of doing all lot of projects you know there is some people resume is full of projects you know and that they have done this they have done that but nobody ask how come in a short time somebody is able to do so many projects and understand it well it is better you do fewer projects fewer things with a greater grasp and kind of a come out with the creative solution the elegant symbol solution you know the elegance you know when you say elegant it is a qualitative word you know we cannot kind of put numbers you know how to assess something is elegant but then it appeals that solution appeals something is elegant the music is elegant the way somebody kind of dress is elegant or when you look at the nature it is kind of beautiful and that can be applied that is a little bit qualitative aspect but then we are able to judge that something is elegant or not so that is just a kind of not justifying the fact that I am not able to kind of do lot of case study I can do it I have enough maybe I can kind of do a course full of case study there is no issue I have so much talk with me so that is not the point but that does not educate you increase your depth of knowledge and so on. So I am trying to balance it out you know now I am trying to you know stress on the device technology the programming language even with the programming language I have emphasised what it means what this construct means and what equations it creates what logical structure it creates and so on rather than you know simply dwelling on the all kinds of syntax and all kinds of jugglery with the syntax there is no point you know there is for a for an expert person even a symbol tool would suffice you know you have a very good photographer he is able to take a good photograph with a maybe a simpler camera but given to a novice even the most advanced camera he will not be able to do that that is true with any tool so the sophistication of the tool would not guarantee that what you design will be kind of efficient, elegant, fault tolerant and all that that comes with expertise the creativity and the logical thinking and systematic working and all that. So that you should keep in mind so my plan is now to complete this programmable logic devices I did not start it because we will be stuck in between it might take 2 or 3 lectures so we will handle the evolution of it the historical evolution of it the simple PLDs which are very rarely used nowadays but maybe there is a use in some cases for it and there is a complex PLD again the application is limited then we will have one part of the VHDL which is remaining is the test bench and there is another part called functions and procedure if time permits I will take it but it is one part of the language wherein it is very similar to a programming sequential programming language of course there is something called operator overloading which is related to synthesis but with whatever I have discussed you can kind of grasp it then we will go on with the FPGAs then we will play with the tool and the case studies and that should kind of wind up you know put everything together and give you a complete picture of designing the digital system practically and it will keep you to kind of start in the path of digital design I would not say that will kind of make you an expert in the front end VLSI design or front end FPGA design but that is a good starting point so that you can continue you can learn you can practice and do well so please now like we have covered almost two third part of the course the last part is coming up so please review whatever we have done learn well I wish you all the best and thank you.