 The first items we're going to look at is how we move closer to a true DSP. So if we look at the core itself, you have this on the flyer that's in front of you. Right in the middle of the core, the block diagram of the core, you have the prefetch unit, the processing centre and the load store. Felly, ydych chi'n gweithio'r bobl, yma yma y ddweud y ddweud y ddweud y ddweud. Felly, mae'n 32-bit ychydig, ond mae'n meddwl i'r 64-bit argymdeithasol ar gyfer 32-bit. This is because, inside the prefetch unit, we now separate the instructions out into two 32-bit streams. So, this is the part of what we call dual issue. So, two instructions come in, on your 64-bit bus. Cymreventu hynny yn rhan gyntaf maeth o y llwylio dw i ddim. Efallai yma yn meddygol. Mae'r rhai llwygarau ac ydw'n meddwl am boledigaethu cerddau wedi bod hi yn cyfnodd, cofioidd, ac nesaf i unrhyw faelo iawn i ddim o'r llwyster dda mewn dwi'n golygu o'r difech mi ar y swydd. Felly, mae'r gael nhw'n gweld o'r llwyfiau syndwiskol, mwy equityr i'r milwyr syndwiskol, oedyn ni wedi bod hynny oedd ymyl yn ddiddordeb ac yn teimlo gynnwys oedyn oedyn yn hynny. Bydd eich gynnwys. Ond bydd eich gynnwys. Fy oed yn gallu'n lliwyddoch chi. Efallai, yn lliwyddoch chi'n gynnwys canio'n digwydd. Felly, mae'n mynd i, os ydych chi,'ll mai yn ei wneud, mae'n iawn gan bwynt'r ddiolchol, mae'r gweithio rhai gyd yn ysbeth, o'r ffordd wych yn cood o marchdain, dweud i'r Rh balloon honno'r gwirio diwg gweithio'r cyhoedd. Mae'n rhan o'r cyfgau sydd wedi sicr o fe fyddio y gorfod yr hyn yn ysbydd humud this dual issue scenario at all times. To make sure you're getting the best performance inside the device. So if we compare that now to the Cortex M4, a single load or store instruction will take about two cycles, typically. If you're doing multiple then it's M plus one cycles. Your Cortex M7 can now do two in parallel. So this is all happening simultaneously. For you, as the customer or as the software engineer, you do have to put your faith into the C compiler a lot here. Your C compiler is going to manage this for you. If you set your optimization to high, your C compiler will rearrange your code to maximize this feature, which means debugging your code becomes a lot more difficult. So you will have to weigh up the balance between the ability to debug and the optimization level you're going to use at the start of your project. You can probably change it later and then revalidate your code. But if you want to try and debug sensibly with the code in a fairly similar order to what you've written it in, then you cannot set your optimization too high in the compiler at the start of your project. So the compiler will manage all of this for you. So you shouldn't have to do anything different as the software engineer. So that provides us with our superscalar architecture, where we can execute two instructions in a single cycle. So that's where that feature comes from. So that brings us a lot closer to how a DSP works in the TIAD world, things like that. So that's pretty much how they're doing things inside there. The second feature we have to bring us closer to a DSP is the zero overhead loops. So again, in this intelligent part, the prefix unit, when these instructions are coming in, the BTAC part with the feedback from the data processing unit are always working out where the jumps are going to go to and where the links need to be brought in from. And all this is going to manage it so that you can do a single cycle branch and jump at the same time. Because you have the two instructions, this will analyse it in the prefix stage before it gets to the processing unit. And it will make sure that that stream is your branch and the alternate jump is sat on the second branch already in the processing pipeline at the same time. So you can pretty much execute a branch with jump in one cycle. If we compare that to the Cortex-M4, it used to take about three cycles and that was with branch speculation enabled inside the Cortex-M4 core. So you've now gone from a three cycle jump to a one cycle jump inside the device. So it's quite a big overhead there with those two features to really up your processing performance of the device. So that means the second feature that takes us closer to a proper DSP.