 Hello and welcome to this presentation of the STM32L4 power controller. The STM32L4's power management functions and all power modes will also be covered in this presentation. Please note that this presentation has been written for STM32L47X48X devices. Key differences with other devices are indicated at the end of the presentation unless otherwise specified. STM32L4 devices feature flex power control which increases flexibility in power mode management and further reduces the overall application consumption. Run mode can support a system clock running at up to 80 MHz with only 120 microamps per MHz. At 26 MHz the consumption is even lower, 100 microamps per MHz. STM32L4 devices support 8 main low power modes. Low power run, sleep, low power sleep, stop zero, stop one, stop two, standby and shutdown modes. Each mode can be configured in many ways, providing several additional sub modes. In addition, STM32L4 devices support a battery backup domain called VBAT. The high flexibility in power management provides both high performance with a Cormac score equal to 273 together with outstanding power efficiency demonstrated by the ULP bench score equal to 150. The STM32L4 has several key features related to power management. Several low power modes, down to 30 nanoamps while it is still possible to wake up the MCU with an event on an I.O. For only 350 nanoamps, 32 kilobytes of SRAM can be retained. A large number of peripherals can wake up from the various low power modes. Dynamic consumption is down to 100 microamps per MHz, executing from flash memory. A battery backup domain called VBAT including the RTC and certain backup registers. Several power supplies are independent, allowing you to reduce MCU power consumption while some peripherals are supplied at higher voltages. Thanks to the large number of power modes, STM32L4 devices offer high flexibility to minimize the power consumption and adjust it depending on active peripherals, required performance and needed wake-up sources. STM32 devices have several independent power supplies, which can be set at different voltages or tied together. The main power supply is VDD, supplying almost all IOs except for 14 IOs of port G. VDD also supplies the reset block, temperature sensor and all internal clock sources. In addition, it supplies the standby circuitry, which includes the wake-up logic and independent watchdog. VDD supplies voltage regulators, which provide the V-core supply. V-core supplies most of the digital peripherals, SRAMs and flash. STM32L4MCUs feature several independent supplies for peripherals. VDDA for the analog peripherals, VDDUSB for the USB transceiver, and VDDIO2, which supplies the 14 IOs on port G. The VLCD pin provides the LCD common and segments reference voltage. The VRF plus pin provides the reference voltage to the analog to digital and to digital to analog converters and can be used as an external buffer reference for the application. A backup battery can be connected to the VBAT pin to supply the backup domain. The main power supply VDD ensures full feature operation in all power modes from 1.71 up to 3.6 volts, allowing it to be supplied by an external 1.8 volt regulator. Device functionality is guaranteed down to 1.6 volts, the minimum voltage after which a brownout reset is generated. Other independent supplies are provided to allow peripherals to operate at a different voltage. The analog power supply VDDA can be connected to any voltage other than VDD. When the analog to digital converters or comparators are used, the VDDA voltage must be greater than 1.62 volts. When the digital to analog converters or operational amplifiers are used, VDDA must be greater than 1.8 volts. When the voltage reference buffer is used, VDDA must be greater than 2.4 volts. The USB power supply VDDUSB can be connected to any voltage other than VDD. When the USB is used, VDDUSB must be greater than 3 volts. 14 IOs of port G from PG-15 to PG-2 are supplied by VDDIO2 independently from VDD. When these IOs are used, VDDIO2 can be as low as 1.08 volts. Several functions are available on these IOs. I2C, SPI, serial audio interface, use arts and timers. The number of available IOs depends on the package. A backup domain is supplied by VBAT, which must be greater than 1.55 volts. The backup domain contains the RTC, the 32.768 kHz LSE external oscillator, and the 128-byte backup registers. The LCD reference voltage can be provided either by an external supply voltage or by the embedded voltage step-up converter. This reference is independent from the VDD voltage, ensuring the same LCD contrast regardless of the VDD value. VLCD is multiplexed with the PC3 pin, which can be used as a GPIO when the LCD is not used. The ADC and DAC voltage references can be provided either by an external supply voltage or by the internal reference buffer. This allows us to improve converter's performance by providing an isolated and independent reference voltage. The Vref plus pin and thus the internal voltage reference is not available on low pin count packages. In those packages, the Vref plus is double bonded with VDDA and the internal voltage buffer must be kept disabled. The voltage reference can be provided through the VDDA pin in those packages. As a general requirement, the VDD power supply has to be provided first and released last. More precisely, during the power on phase, the following power sequence requirements must be respected. When VDD is below 1 volt, other power supplies, VDDA, VDDIO2, VDDUSB and VLCD must remain below VDD plus 300 millivolts. When VDD is above 1 volt, all power supplies become independent. During the power down phase, VDD has to be switched off at the same time or after other power supplies. But VDD can temporarily become lower than other supplies, provided that the energy absorbed by the MCU during this transient phase remains below 1 millijoule. Refer to the application note AN4555 for more details on the power supply sequencing. The STM32L4 MCU embeds four peripheral voltage monitors to detect if the independent supply is present or not. These comparators have wake up from stop mode capability. The PVM1 compares the VDDUSB voltage with the 1.22 volts threshold. The PVM2 compares the VDDIO2 voltage with the 0.96 volt threshold. The PVM3 compares the VDDA voltage with the 1.65 volt threshold intended for the comparators and analog to digital converters. The PVM4 compares the VDDA voltage with the 1.82 volt threshold intended for the operational amplifiers and digital to analog converters. To guarantee any of the supply sequences on the application, power isolation has been implemented and is active by default. It is the role of software to enable the needed supplies by removing the power isolation. The power supply supervisor guarantees a safe and ultra low power reset management. STM32L4 devices embed an ultra low power brownout reset which is always enabled in all power modes except shutdown mode. The BOR ensures reset generation as soon as the MCU drops below the selected threshold regardless of the VDD slope. 5 thresholds from 1.7 to 2.95 volts are selected by option byte programmed in flash memory. A power voltage detector can generate and interrupt when VDD crosses the selected threshold. The PVD can be enabled in all modes except standby and shutdown modes. 7 thresholds can be selected by software. In addition, comparisons can be done with an external pin. The BOR consumption with the 1.7 volt threshold is included in the datasheet. Two embedded linear voltage regulators supply all the digital circuitries except for the standby circuitry and the backup domain. The regulator output voltage or V-Core can be programmed by software to two different values depending on the performance and the power consumption requirements. This is called dynamic voltage scaling. Depending on the application mode, V-Core is provided either by the main voltage regulator for run and sleep modes or by the low power regulator for low power run, low power sleep, stop 0, stop 1, and stop 2 modes. The regulators are off in standby and shutdown mode. When SRAM 2 content is preserved in standby mode, the low power regulator remains on and provides the SRAM 2 supply. In run mode, the voltage scaling range 1 is the high performance range, allowing a system clock up to 80 MHz. All peripherals can be activated. All clocks can be enabled. The run mode range 1 consumption is 131 microamps per MHz at 80 MHz from flash memory with the ART accelerator enabled. In run mode, the voltage scaling range 2 is the medium performance range, allowing a system clock up to 26 MHz. When executing from SRAM, the flash consumption can be saved by configuring the flash in power down mode and by gating its clock off. All peripherals can be activated except the USB OTG and random number generator. All clocks can be enabled. The run mode range 2 consumption is 110 microamps per MHz at 26 MHz from SRAM. In low power run mode, the main regulator is off and the low power regulator supplies the logic, allowing a system clock up to 2 MHz. When executing from SRAM, the flash consumption can be reduced by configuring the flash memory in power down mode and by gating its clock off. All peripherals can be activated except the USB OTG and random number generator. All clocks can be enabled. At 2 MHz, there is no limitation regarding the number of peripherals that can be activated. The low power run mode consumption is 135 microamps per MHz at 2 MHz when executing from flash memory with the ART accelerator enabled. It is 112 microamps per MHz at 2 MHz when executing from SRAM 1. The I2C, USART, LPUART and SWPMI clocks can be based on the internal high speed oscillator at 16 MHz. The run mode thanks to voltage scaling and the low power run modes offer flexibility between required performance and consumption. In run mode range 1, the system clock is limited to 80 MHz and the internal and external oscillators and the PLL can be used. In run mode range 2, the system clock is limited to 26 MHz and the internal and external oscillators as well as the PLL can be used but must be limited to 26 MHz. In low power run mode, the system clock must be limited to 2 MHz. Each peripheral clock can be configured to be on or off in run and low power run modes. By default, all peripheral clocks are off except the flash interface clock. The SRAM 1 and SRAM 2 clocks are always on in run mode. When running from SRAM 1 or SRAM 2 in run or low power run modes, the flash memory can be put in power down mode thanks to software and the flash clock can be switched off. The flash memory must not be accessed when it is switched off. Consequently, interrupts must be mapped in SRAM using the Cortex-M4 vector table offset register. The current consumption in run or low power run modes depends on several parameters. First, the executed binary code. That means the program itself plus the compiler impact. Then it depends on the program location in the memory, the device software configuration, the IOPIN loading and switching rate, the temperature and so on. The consumption also depends on if the code is executed from flash memory or from SRAM. When code is executed from flash, the energy efficiency is better when the flash accelerator is enabled. When code is executed from SRAM, the energy efficiency is better when executing from SRAM 2. The consumption in run mode can be optimized down to low frequency thanks to low power run mode. Enabling the art accelerator increases performance but also reduces the dynamic consumption. Best consumption is most often reached when the instruction cache is on, data cache is on and prefetch buffer is off. As this configuration reduces, the number of flash memory accesses. The small flash dynamic consumption allows a small consumption each time the firmware needs to access the flash memory. Consumptions from SRAM 1 and SRAM 2 are quite similar, but SRAM 2 is much more power efficient than SRAM 1 when not remapped at address zero thanks to its zero weight state access. Sleep and low power sleep modes allow all peripherals to be used and feature the fastest wake up time. In these modes the CPU is stopped and each peripheral clock can be configured by software to be gated on or off during the sleep and low power sleep modes. These modes are entered by executing the assembler instruction, wait for interrupt or wait for event. When executed in low power run mode, the device enters low power sleep mode. Depending on the sleep on exit bit configuration in the Cortex-M4 system control register, the MCU enters sleep mode as soon as the instruction is executed or as soon as it exits the lowest priority interrupt subroutine. This last configuration allows you to save time and consumption by saving the need to pop and push the stack. Batch acquisition mode is an optimized mode for transferring data. Only the needed communication peripheral plus 1DMA plus SRAM 1 or SRAM 2 are configured with clock enable in sleep mode. Flash memory is put in power down mode and the flash memory clock is gated off during sleep mode. Then it can enter either sleep or low power sleep mode. Note that the I2C clock can be at 16 MHz even in low power sleep mode, allowing support for 1 MHz fast mode plus. The USART and LPU art clocks can also be based on the high speed internal oscillator. Typical applications are sensor hubs. In sleep mode the CPU clocks are off. In range 1 the system clock is up to 80 MHz. In range 2 it is up to 26 MHz. By default the SRAM 1 and SRAM 2 clocks are enabled. They can be gated off during sleep mode by software. All peripherals can be activated in range 1. In range 2 all peripherals can be activated except the USB OTG and random number generator. The sleep mode consumption is 37 microamps per MHz in range 1 at 80 MHz with the flash memory on. In low power sleep mode the CPU clocks are off and the logic is supplied by the low power regulator. The system clock is up to 2 MHz. Flash memory can be configured in power down and can be gated off. SRAM 1 and SRAM 2 can be gated off. All peripherals can be activated except the USB OTG and random number generator. The low power sleep mode consumption is 40 microamps per MHz at 2 MHz with flash memory and SRAM off. STM32L4 devices feature 3 stop modes. Stop 0, 1 and 2 which are the lowest power modes with full retention and only a 0.7 microsecond wake up time to run mode at 48 MHz. The contents of SRAM 1, SRAM 2 and all peripherals registers are preserved in stop modes. All high speed clocks are stopped. The 32.768 kHz external oscillator and 32 kHz internal oscillator can be enabled. Several peripherals can be active and wake up from stop mode. System clock on wake up can be the internal high speed and multi speed oscillators up to 48 MHz with only a 0.7 microsecond wake up time from SRAM or 5 microseconds from flash. Stop 2 consumption is lower than stop 1 but stops 0 and 1 support more active peripherals. In stop 0 mode the system clock is frozen and all high speed clocks are powered down. The RTC clocked by the internal or external low speed oscillator can be activated. The brownout reset is always enabled. Most of the peripheral clocks are gated off. Several peripherals can be functional in stop 0 mode. Power voltage detector, peripherals voltage monitor, LCD controller, digital to analog converters, operational amplifiers, comparators, independent watchdog, low power timers, I2C, UART and low power UART. The events from all IOs can wake up from stop 0 mode plus the interrupt generated by the active peripherals. In addition SWPMI and USB can wake up from stop 0 mode. The I2C and UART or LP UART can switch the HSI16 on during the stop mode in order to recognize their wake up condition. The stop 0 mode consumption is 110 microamps typical at 3 volts. The wake up time is 0.7 microseconds when the system clock at wake up is MSI at 48 megahertz and the code is executed from SRAM. Stop 1 mode is very similar to stop 0 except that the power figures are much lower as the main regulator is stopped and replaced by the low power regulator. The stop 1 mode consumption without RTC is 6.6 microamps typical at 3 volts. The wake up time is 4 microseconds when the system clock at wake up is MSI at 48 megahertz and the code is executed from SRAM. In stop 2 mode the system clock is frozen and all high speed clocks are powered down. The RTC clocked by the internal or external low speed oscillator can be activated. The brownout reset is always enabled. Most of the peripheral clocks are gated off. Several peripherals can be functional in stop 2 mode. Power voltage detector, peripheral voltage monitors, LCD controller, comparators, independent watchdog, low power timer 1, I2C3 and the low power UART. The events from all IOs can wake up from stop 2 mode plus the interrupt generated by the active peripherals. The I2C3 and LPUART can switch the HSI16 on during stop mode in order to recognize their wake up condition. The consumption in stop 2 mode without the RTC is 1.2 microamps typical at 3 volts. The wake up time is 5 microseconds when the system clock at wake up is MSI at 48 megahertz and the code is executed from SRAM. When comparing stop modes stop 1 mode consumption is higher than stop 2 mode consumption but the wake up time is shorter and the number of active peripherals is higher. Stop 0 mode keeps the main regulator enabled allowing a very short wake up time lower than 1 microsecond when restarting from the RAM to the expense of a higher consumption than stop 1. It is possible to wake up from stop 0 or 1 mode with the USB resume from suspend event or with attached detection but it is not supported in stop 2 mode. An SWPMI resume from suspend event can also wake up the MCU from stop 0 or 1 mode but not from stop 2. The I2C address recognition is functional in both stop modes and can generate a wake up event in case of an address match. Only one I2C is supported in stop 2 versus three I2C's in other stops. The UART byte reception is functional in both stop modes and can generate a wake up event in case of start detection or byte reception or address match event. Only the low power UART is supported in stop 2 mode. In other stop modes all 5 UARTs and the low power UART can generate a wake up event. When clocked by the internal or external low speed oscillator or when clocked by an external pin the low power timer can wake up the MCU with all its events. In stop 0 or 1 mode both low power timers are supported whereas only LP-TIM-1 is supported in stop 2 mode. The standby mode is the lowest power mode in which 32 kilobytes of SRAM-2 can be retained. The automatic switch from VDD to VBAT is supported and the IO's level can be configured by independent pull up and pull down circuitry. By default the voltage regulators are in power down mode and the SRAMs and the peripherals registers are lost. The 128 byte backup registers are always retained. Thanks to software it is possible to retain 32 kilobytes of SRAM-2. The ultra low power brownout reset is always on to ensure a safe reset regardless of the VDD slope. Each IO can be configured with or without a pull up or pull down which is applied and released thanks to the APC control bit. This allows you to control the input state of external components even during standby mode. 5 wake up pins are available to wake up the device from standby mode. The polarity of each of the 5 wake up pins is configurable. The wake up clock is MSI with a frequency configurable from 1 to 8 MHz. In standby mode with SRAM-2 the main regulator is powered down and the low power regulator supplies the SRAM-2 to preserve its content. The RTC clocked by the internal or external low speed oscillator can be activated. The brownout reset is always enabled. The independent watchdog can also be enabled in standby mode. Reset, brownout reset, RTC and tamper detection, independent watchdog and any event on the 5 wake up pins can exit the MCU from standby mode. The standby with SRAM-2 consumption without the RTC is around 390 nanoamps typical at 3 volts. The wake up time is approximately 4 microseconds. In standby mode without SRAM-2 the main regulator and the low power regulator are powered down. The RTC clocked by the internal or external low speed oscillator can be activated. The brownout reset is always enabled. The independent watchdog can also be enabled in standby mode. The wake up events are the same as those described in standby mode with SRAM-2. The standby consumption without RTC is 150 nanoamps typical at 3 volts. The wake up time is approximately 14 microseconds. The shutdown mode is the lowest power mode of the STM32L4 with only 30 nanoamps at 1.8 volts. This mode is similar to standby mode but without any power monitoring. The brownout reset is disabled and the switch to VBAT is not supported in shutdown mode. Hence, the product state is not guaranteed in case the power supply is lowered below 1.6 volts. The LSI is not available and consequently the independent watchdog is also not available. A brownout reset is generated when the device exits shutdown mode. All registers are reset except those in the backup domain and a reset signal is generated on the pad. The 128-byte backup registers are retained in shutdown mode. The wake up sources are the 5 wake up pins and the RTC. When exiting shutdown mode, the wake up clock is MSI at 4 MHz. In shutdown mode, the main regulator and the low power regulator are powered down. The RTC clocked by the external low speed oscillator can be activated. The brownout reset is deactivated. Only the external low speed clock can be enabled. The wake up events are the RTC and TAMP events, the reset and the 5 wake up pins. The shutdown consumption without RTC is around 60 nanoamps typical at 3 volts. The wake up time is approximately 250 microseconds. Here you can see the summary of all the STM32L4 power modes. From run mode, it is possible to access all low power modes except low power sleep mode. In order to go into low power sleep mode, it is required to move first to low power run mode and execute a wait for interrupt or wait for event instruction while the regulator is the low power regulator. On the other hand, when exiting low power sleep mode, the STM32L4 is in low power run mode. When the device is in low power run mode, it is possible to go into all low power modes except sleep, stop zero and stop two modes. Sleep, stop zero or stop two modes can only be entered from run mode. If the device enters stop one mode from low power run mode, it will exit in low power run mode. If the device enters standby or shutdown from low power run mode, it will exit in run mode. The backup domain allows you to keep the RTC functional and to preserve the backup registers in case the VDD supply is down, thanks to a backup battery connected to the VBAT pin. The backup domain contains the RTC clocked by the low speed external oscillator at 32.768 kHz. Three tamper pins are functional in VBAT mode and will erase the 128-byte backup registers also included in the VBAT domain in case of intrusion detection. The backup domain also contains the RTC clocked control logic. In case VDD drops below a certain threshold, the backup domain power supply automatically switches to VBAT. When VDD is back to normal, the backup domain power supply automatically switches back to VDD. The VBAT voltage is internally connected to an ADC input channel in order to monitor the backup battery level. When VDD is present, the battery connected to VBAT can be charged from the VDD supply. The battery charging feature allows charging of a supercap connected to a VBAT pin through an internal resistor when VDD supply is present. The charging is enabled by software and is done either through a 5 kilo ohm or 1.5 kilo ohm resistor depending on software. Battery charging is automatically disabled in VBAT mode. In VBAT mode, the entire MCU is in power down mode except the backup domain including the 128-byte backup registers, RTC, and external low speed clock. The consumption from the VBAT pin is approximately 6 nanoamps without the RTC at 3 volts and 500 nanoamps with the RTC. Three bits are available in the flash option bytes to prohibit a given low power mode. When cleared, an option bit configures reset generation when entering shutdown mode. Another bit configures reset generation when entering standby mode and the last bit configures reset generation when entering stop modes. Three bits are available in the debug control center in order to allow debugging in sleep, stop, standby, and shutdown modes. When the related bit is set, the regulator is kept on in standby and shutdown modes and the HCLK and FCLK clocks remain on to keep the debugger alive. This maintains the connection with the debugger during the low power modes and continues debugging after wake up. Remember to clear these bits when the MCU is not under debug because the consumption is higher in all low power modes when these bits are set due to the fact they force the clocks and the regulators to remain enabled. In addition to this training, you can refer to the reset and clock control and interrupts trainings as well as those for all the peripherals with wake up from stop capability. For more details, please refer to application note STM32L4 Ultra Low Power Features Overview. This slide presents the key consumption differences between STM32L4 devices. This slide presents the key differences in ULP bench scores between STM32L4 devices.