 Namaste, welcome to the session design of synchronous counter. At the end of the session students will be able to analyze and design synchronous counters. First of all take a pause here and recall what do you mean by asynchronous counters. So asynchronous counter is the simplest type of counter and also known as serial or series counter. In this type of counters output of first flip-flop drives the clock for the second flip-flop and output of second flip-flop drives the output for the third flip-flop and so on. The synchronous counter is also known as parallel counter since all flip-flops are triggered simultaneously by a clock pulse. We know that flip-flop has two states therefore a group of n number of flip-flop will have two raise to n states that will help us to design a synchronous counter. In synchronous counter also we have different types like up counter, down counter and up down counter. Now let us design a two bit synchronous up counter. Whenever it is two bit means we have to use two flip-flops. So let us write the truth table first. So in the truth table you can see clock input then output and state changes. So in the output we have output of two flip-flops represented as q2 and q1. So from this truth table you can observe that q1 output make the transition always but output q2 that is second flip-flops output make the changes only when output of q1 is 1 then it will make the transition from 0 to 1 and again when output of q1 is 1 here it will make the transition from 1 to 0. So cycle repeats and in the last column you can observe that the state changes are represented by NC which means no change and T means toggle. So based on the particular state and the clock input there may be no change or toggle in the state change. So based on this truth table we are drawing a logic diagram here. So here as it is a synchronous counter all the flip-flops are simultaneously clocked through a single clock input then as first flip-flop make the transition always. So it is connected in the toggle mode by connecting j1 and k1 to the high input then next flip-flop makes the transition when q1 output is high. So here we are connecting high output that is q1 from the first flip-flop to the input of the next flip-flop to the j2 and k2 through this AND gate. So let us see the operation of these two bits in corona sub counter. Let us consider initially the state is 0 0 so output q1 is 0 and q2 is 0. So q1 output 0 is connected to this AND gate so it gives 0 here. So when j2 is 0 k2 is also 0 then there will be no change. So when next clock pulse is given you can see here q2 remains same but q1 changes the state because here input is high to the next to that when clock pulse is given. So the previous output of q1 is 1 so 1 into 1 it is given as a 1 1 to the j2 k2 so it comes in a toggle mode. So as you can see here and the q2 output changes 0 to 1 to the next clock pulse the output of q1 is 0 here and that 0 is given to the j2 so it remains in a same state. So q2 remains in same state that is 1 but up due to this high input the q1 make the changes that is 0 to 1 and hence it is decoded as 3. So in this way this two bit up counter counts in ascending order from 0 0 0 1 1 0 1 1 so here we are decoding from q2 to q1 in decimal as 0 1 2 3. Now let us consider the last state of q1 and q2 is 1 1 and when next clock pulse is given what happens is as q1 is 1 so 1 1 is given to the j2 so it will make the transition so q2 will change from 1 to 0 and the first flip flop is already in a toggle mode so it will also make the transition from 1 to 0 so again cycle get repeated. So this can be observed in from this timing diagram so for the first clock it make the transition from 0 0 to 0 1 with respect to the next clock it makes the transition from 0 1 to 1 0 and to the final clock it makes the transition from 1 0 to 1 1 and if next clock is given again cycle get repeated. Now let us design two bit synchronous down count so with the help of truth table so as it is a down counter so it should start counting from the last bit so here we are assuming that it is in a state as 0 0 then it will make the transition 0 0 to 3 that is 1 1 then 2 that is 1 0 and 0 1 as 1 and again cycle repeats so 3 2 1 0 so according to this truth table you can observe that q1 is always making transition from 0 to 1 1 to 0 and 0 to 1 but q2 making transition when q1 output is 0 so here you can observe when q1 output is 0 then only the q2 is making transition from 0 to 1 and when next q1 comes 0 then again you can see there is a transition from 1 to 0 for q2 again you can observe that state changes are no change and toggle so the logic diagram for this two bit synchronous down counter is so the first flip flop should always connected in a toggle mode so that is why j1 and k1 are always connected to the high then next flip flop is making the transition when output of q1 is 0 so that is why the complemented output from the first flip flop that is q1 bar is connected to the AND gate with respect to this high input and connected to the j2 and k2 so let us assume the initial output is 0 0 here and this is decoded as 0 when next clock pulse is given then what happens is when q1 and q2 are 0 0 q1 bar will be 1 so one of the input is 1 and one more input is 1 so 1 is given to j2 and k2 so it comes in toggle mode so that is why the output q2 changes from 0 to 1 and the first flip flop is already in a toggle mode so it will also make the transition from 0 to 1 so this is decoded as 3 then to the next clock pulse as we have output q1 and q2 1 1 so q1 bar will be 0 so that 0 is given to this AND gate and that is given to the j2 k2 so it is repeating the last state only so 1 to 1 but the first flip flop is already in a toggle mode so it will make the transition from 1 to 0 so this representing 1 0 and decoded as 2 now the condition here is q1 is 0 so q1 bar will be 1 so when it is 1 output of AND gate will be 1 to j2 and k2 so the q2 will make the transition 1 to 0 and q1 will always toggle so the output now is 0 1 representing decimal 1 when next clock pulse is given you can observe that output of q1 is 1 so q1 bar will be 0 so as 0 is given to j2 and k2 it will repeat the last state as it is 0 0 and q1 output will also make the transition 1 to 0 hence the cycle get repeated and we get this output as down counting now same thing is represented through the timing diagram so with the first clock it makes the transition from 0 0 to 1 1 and to the next clock it makes the transition from 1 1 to 1 0 and to the next clock it makes the transition from 1 0 to 0 1 and when again you are giving a clock it will make the transition from 0 1 to 0 0 hence cycle get repeated now let us design 2 bit synchronous up down counter so 2 bit synchronous up down counter means it is the combination of up counter and down counter so for up counter the upper output that is q1 with the AND gate is working as a up counter and the q1 bar along with this AND gate working as a down counter when the output of AND gate is combined with OR gate and given as a input to the j2 k2 along with this mode control with NOT gate the circuit will work as a synchronous up down counter so here M represents mode control so when mode control M is 1 so upper AND gate will always activated so it will work as a up counter and at the same time lower AND gate will be deactivated and when M is equal to 0 so upper AND gate will be deactivated and due to this NOT gate 1 is given to the lower AND gate and it is always activated and hence it works as a down counter so in this way this circuit works as a 2 bit synchronous up down counter so in this way we can design 3 bit synchronous 4 bit synchronous up counter down counter or up down counter these are the references thank you.