 Hello and welcome to this presentation of the hash processor. The hash peripheral is in charge of efficient computing of the message digest. A digest is a fixed length value computed from an input message. A digest is unique. It is virtually impossible to find two messages with the same digest. The original message cannot be retrieved from its digest. Hash digests and hash-based message authentication code, or HMAC, are widely used in communications since they are used to guarantee the integrity and authentication of a transfer. The hash processor supports widely used hash functions, including message digest 5 or MD5, secure hash algorithm or SHA1, and the more recent SHA2 with its 224 and 256-bit digest length versions. A hash can also be generated with a secret key to produce a message authentication code, or MAC. The processor supports bit, byte, and half-word swapping. It also supports automatic padding of input data for block alignment. The processor can be used in conjunction with the DMA for automatic processor feeding. All supported hash functions work on 512-bit blocks of data. The input message is split as many times as needed to feed the hash processor. Subsequent blocks are computed sequentially. MD5 is the less robust version with only a 128-bit digest. The SHA standard has two versions, SHA1 and the more recent SHA2, with its 224 and 256-bit digest length versions. The hash-based message authentication code, or HMAC, is used to authenticate messages and verify their integrity. The HMAC function consists of two nested hash functions with a secret key that is shared by the sender and the receiver. The hash function involved in the HMAC computation can be any one supported by the peripheral. MD5, SHA1, or SHA2. The hash processor complies with the international standards for secure hash algorithms, or SHA, message digest algorithms, or MD5, and for message authentication code, or MAC. This simplified block diagram of the hash processor shows the basic data flow and control module. The hash processor processes 512-bit data blocks and generates digests of up to 256 bits, depending on the algorithm. Input data may be swapped before entering the core unit, where they will be processed, to generate a simple hash or a message authentication code, or MAC. An interrupt in the nested-vectored interrupt controller, or NVIC, is triggered when a hash digest has been successfully calculated, or when the hash processor is ready to accept a new block of data. Indirect memory access, or DMA mode, requests are generated internally for incoming data. The DMA channel must be configured in memory to peripheral mode with a data size equal to 512 bits. These are the times it takes to process a single block of data, depending on the chosen algorithms. HCLK is the CPU clock and can go as high as 80 MHz. Note that the main benefit of using a hardware accelerator is to increase speed and save power compared to a full software implementation of the hash functions. Here is an overview of the status of the hash processor in each of the low power modes. Hash operations are not possible when the device is in stop mode. This is a list of peripherals related to the hash processor. Please refer to AES peripheral trainings if you want to know more about cryptographic functions. Refer to training on the DMA peripheral for information on how to configure the hash channel. For more details, please refer to this user manual available on our website.