 Hello, and welcome to this presentation of the STM32G0 Reset and Clock Controller. The RCC unit implemented in the STM32G0 offers new features with regard to the STM32F0 microcontrollers. The NRST pin has three possible usages. The first usage is a reset input used by an external logic to signal a reset condition to the STM32G0. The second usage is a reset input and output. Any valid reset signal on the pin is propagated to device internal logic, and all internal reset sources are externally driven through a pulse generator to this pin. The third usage is a GPIO. In this mode, the pin can be used as standard GPIO. Reset is only possible from the device's internal reset sources. If enabled in the option bytes, the reset holder option can be used to ensure that the pin is pulled low until its voltage meets the VIL threshold. The PLL has three post dividers providing three independent outputs. PLL P-Clock, PLL Q-Clock, and PLL R-Clock. The clock security system, or CSS, monitors the LSE and detect failures. If the low speed external 32.768 kHz oscillator, or LSE, is used as a system clock and a failure of LSE clock is detected, the system clock switches automatically to the low speed internal 32 kHz RSE oscillator named LSI. HSI-SIS is the high speed internal 16 MHz RSE oscillator, or HSI-16, divided by a programmable ratio in range 1 to 128. PLL Q-Clock is selectable for high speed TIM 1 and TIM 15 timers. Its frequency must be set so as not to exceed 128 MHz. This is twice the maximum frequency of the Cortex M0+. The STM32G0 reset and clock controller manages system and peripheral clocks. STM32G0 devices embed two internal oscillators, two oscillators for an external crystal or resonator, and one phase locked loop, or PLL. Many peripherals have their own clock, independent of the system clock. The RCC also manages the various resets present in the device. The STM32G0 RCC provides high flexibility in the choice of clock sources, which allows the system designer to meet both power consumption and accuracy requirements. The numerous independent peripheral clocks allow a designer to adjust the system power consumption without impacting the communication baud rates, and also keep some peripherals active in low power modes. Finally, the RCC provides safe and flexible reset management. Safe and flexible reset management without any need for external components reduces application costs. The RCC manages three types of resets. The system reset, the power reset, and the backup domain reset. The peripherals have individual reset control bits. The first type of reset is the system reset, which resets all the registers except certain registers for the reset and clock controller. It also does not reset the RTC domain. The system reset sources are the external reset generated by a low level on the NRST pin, a window watchdog event, an independent watchdog event, a software reset request, a low power mode security reset, which is generated when stop, standby, or shutdown mode is entered, but is prohibited by the option byte configuration, an option byte loader reset, and a brownout or power on reset. The reset source flag can be found in the RCC control and status register. Two fields in the option bytes are used to configure the NRST pin. NRST mode selects the operation mode of the NRST pin, input or output reset, input only reset, or GPIO. IRHEN stands for internal reset holder enable. When this mode is enabled, the NRST pin is driven low until its voltage level goes under the voltage input low threshold. Here is the simplified block diagram of the system reset. All internal reset sources provide a reset signal on the NRST pin, which can be used to reset other components of the application board. In addition, no external reset circuitry is needed due to the internal glitch filter and the safe power monitoring feature, which guarantees the reset of the application when VDD is below the selected threshold. The internal pull-up on the NRST pin, which maintains a high level when no reset signal drives it low, is deactivated when an internal reset is driven in order to reduce power consumption under reset. Additionally, except the debug pins and some test pins, all IO pins are placed in analog mode during and after reset to eliminate power consumption through the Schmidt trigger when the IOs are floating under reset and before software initialization. The purpose of the reset holder is to maintain NRST driven low until the voltage level of the signal goes below VIL. This is useful when the NRST line has an important capacitive load. The second type of reset is the power reset. The brownout reset, or BOR, resets all registers except those in the RTC domain powered by VBAT, which contains the RTC, the backup registers, and the external low-speed oscillator. When exiting standby mode, all registers powered by the regulator are reset. When exiting shutdown mode, a brownout reset is generated. The third type of reset is the RTC domain reset, which resets the RTC registers, the backup registers, and the RTC domain control register. This reset occurs when the BDRST bit is set in the RTC domain control register. It also occurs when VDD and VBAT are powered on if both supplies have previously been powered off. The RCC offers a large choice of clock sources, which can be selected depending on low power, accuracy, and performance requirements. STM32G0 devices embed two internal clock sources, a high-speed internal 16 MHz RC oscillator, or HSI16, and a low-speed internal 32 kHz RC oscillator, or LSI. STM32G0 devices embed two oscillators for use with an external crystal or resonator, a high-speed external 4-48 MHz oscillator, or HSE, with a clock security system and a low-speed external 32.768 kHz oscillator, or LSE, also with a clock security system. STM32G0 devices embed a phase-locked loop with three independent outputs for clocking different peripherals at different frequencies. The system clock can be derived from the high-speed internal 16 MHz RC oscillator, or HSI16, the high-speed external 4-48 MHz oscillator, or HSE, the low-speed internal oscillator, or LSI, or the low-speed external oscillator, or LSE. The AHB clock, called H-Clock, is derived by dividing the system clock by a programmable prescalar. The APB clock, called P-Clock, is generated by dividing the AHB clock by a programmable prescalar. The RTC clock is generated by the low-speed external 32.768 kHz oscillator, or LSE, the low-speed internal 32 kHz RC oscillator, or LSI, or the HSE, divided by 32. The LSE can remain enabled in all low-power modes and in VBAT mode, because the LSE belongs to the RTC power domain. The LSI can remain enabled in all modes except shutdown and VBAT modes. Stop modes, i.e. stop 0 and stop 1, stop all the clocks in the V-core domain, and disable the PLL as well as the HSI16 and HSE oscillators. The high-speed internal oscillator is a 16 MHz RC oscillator, which provides 1% accuracy and fast wake-up times. The HSI16 is trimmed during production testing and can also be user-trimmed. The HSI-SIS clock, which is the HSI16 clock divided by HSIDIV, is used as the clock at wake-up from stop 0 or stop 1 modes. HSI16 can be used as a backup clock source, i.e. auxiliary clock. If the HSE crystal oscillator fails, which is detected by the clock security system. The USART1, USART2, LPUART1, CEC, UCPD, and I2C1 peripherals can enable the HSI16 oscillator, even when the MCU is in stop mode. If HSI16 is selected as clock source for that peripheral. This table provides the characteristics of the HSI16 clock. The HSI16 accuracy can be improved by implementing a trimming procedure. By measuring its frequency with the TIM-14, TIM-16, or TIM-17, by clocking the timer by HSI clock and providing precise clock reference like HSE divided by 32 RTC clock or LSE on their Channel 1 input capture. The HSI clock has a typical 1-microsecond start-up time, while the HSE clock has a typical 2-millisecond start-up time. The high-speed external oscillator provides a safe crystal system clock. The HSE supports a 4-48 MHz external crystal or ceramic resonator and also an external source in bypass mode. A clock security system allows an automatic detection of HSE failure. In this case, a non-maskable interrupt is generated and a break input can be sent to timers in order to put critical applications such as motor control in a safe state. When an HSE failure is detected, the HSE oscillator is automatically disabled. If HSE is selected directly or indirectly via PLLR clock selected for SIS clock and HSE selected as PLL input as system clock and a failure of HSE clock is detected, the system clock switches automatically to HSI SIS so the application software does not stop in case of crystal oscillator failure. In external source mode, also called HSE bypass mode, an external clock source must be provided. It can have a frequency of up to 48 MHz. The external, square, sinus or triangle clock signal with 40-60% duty cycle depending on the frequency must drive the OSC in-pin. The OSC out-pin can be used as GPIO or it can be configured as an OSCEN alternate function to provide a signal enabling the stop of the external clock synthesizer when the device enters low power modes. STM32G0 devices embed an ultra low power 32 kHz RC oscillator which is available in all modes except shutdown and V-BAT. The LSI can be used to clock the RTC, the low power timers and the independent watchdog. The LSI consumption is typically 110 nanoamps. The 32.768 kHz low speed external oscillator can be used with external quarts or resonator or with an external clock source in bypass mode. The oscillator driving capability is programmable. Four modes are available from an ultra low power mode with a consumption of only 250 nanoamperes to a high driving mode. A clock security system monitors for failure of the LSI oscillator. If LSI is used as system clock and a failure of LSI clock is detected, the system clock switches automatically to LSI. The CSS is functional in all modes except shutdown and V-BAT. It is also functional under reset. The LSI can be used to clock the RTC and CEC, the USARTS or low power UART peripherals and the low power timers. STM32G0 devices embed a phase locked loop each with three independent outputs. The input clock of the PLL can be selected between HSI-16 and HSE. PLL-Q clock can be used to clock the RNG and timers TIM-1 and TIM-15. PLL-P clock can be used to clock I2S1 and ADC. PLL-R clock can be selected as the system clock called SISCLOCK, which is the root clock for AHB and APB clock domains. Note that PLL-Q clock and PLL-P clock maximum frequencies are larger than the maximum SISCLOCK frequency. RANG1 and RANG2 are two different power ranges that can be programmed in the main regulator in order to optimize the consumption, depending on the system maximum operating frequency. The system clock is selected between the HSI-16, HSE, LSI, LSE, and PLL output. The maximum system clock frequency is 64 MHz. The APB-1 and APB-2 bus frequencies are also up to 64 MHz. The maximum clock source frequency depends on the voltage scaling and power mode. The system clock is limited to 64 MHz in RANG1, 16 MHz in RANG2, and 2 MHz in low-power run or low-power sleep modes. The various clocks can be output on an IO. The microcontroller clock output feature allows you to output on a PIN-1 of these six clocks, HSI-16, HSE, LSI, LSE, SISCLOCK, and PLL clock. The low-speed clock output or LSEO feature allows the output of the LSI or LSE clock on a PIN. The low-speed clock output is available in stop-0, stop-1, standby, and shutdown modes. This is enabled by setting the LSEOEN bit in the RCC BDCR register. Note that LSI is not available in shutdown mode. The dynamic power consumption can be optimized by using peripheral clock gating. Each peripheral clock can be gated on or off in run and low-power run modes. By default, the peripheral's clock is disabled, except the flash memory clock, which is enabled by default. When a peripheral's clock is disabled, the peripheral's registers cannot be read or written. Other registers allow for configuring the peripheral's clock during the stop, sleep, and low-power sleep modes. This also affects stop-0 and stop-1 modes for peripherals with an independent clock active in stop modes. These control bits have no effect if the corresponding peripheral clock enable is cleared. By default, no active peripheral clock is gated in stop, sleep, and low-power sleep modes. When a peripheral is not needed, its clock enable bit should be cleared to reduce the power consumption. This slide lists the RCC interrupts, the LSE and HSE clock security systems, the PLL-RED, and all five oscillator-RED signals can generate an interrupt. In addition to this training, you may find the power control and interrupt controller trainings useful. For more details, please refer to the application note AN2867, an oscillator design guide for STM8S, STM8A, and STM32 microcontrollers, and application note AN5126, which explains how to calibrate STM32G0 internal RC oscillators.