 I am Dr. Rishal Gajbar and in this video lecture we are going to implement 2S to 1 multiplexer circuit by using VaryLock-HDL language. So, at the end of this session you will be able to implement 2S to 1 multiplexer by using VaryLock-HDL. You will also be able to write the test bench in VaryLock to verify the model correctness also. So, the software that we are going to use for the simulation purpose is model sim student edition. You can download the software by using the link which is provided here. It is a free of cost software, so anyone can download and write the VaryLock modules. So, the workflow for this session will be as follows. We will first discuss the VaryLock module for a circuit which is a 2S to 1 multiplexer in this case. Then we will write down the or discuss the test bench and then finally we will verify the simulation results in model sim software. So, before writing the 2S to 1 multiplexer module definition in VaryLock, let us discuss the circuit in detail. So, multiplexer is a combinational circuit which has many inputs, but only one output and there are some select inputs and the value which is provided to the select input particular input will be available at the output, so basically it is like a data selector circuit. So, depending on the select input which is provided here, this output y is connected to one of the inputs and that input will be available at the output y. So, this shows the function table for the 2S to 1 multiplexer and here you can see for a 0 equal to 0, y is equal to i 0. So, whenever you provide a 0 equal to 0, this y is connected to i 0 and y is equal to i 0 in this case and for a 0 equal to 1, you get y equal to i 1 and this y output can be expressed using this logical expression which is equal to a 0 bar and operation with i 0 or operation with a 0 and operation with i 1. So, this is the VaryLock module definition for the 2S to 1 multiplexer, it will start with the module keyword, MUX 2 1 is the name of the module, in the bracket we provide the list of input and outputs. So, there are 3 inputs i 0 i 1 and i 0 and there is one output which is y. In the next 2 line we define explicitly the inputs and outputs by using the input and output keywords. So, the inputs are i 0 i 1 and i 0 and these are defined using the input keyword and the outputs are defined here. So, all the keywords are represented here by using the bold symbol. So, output is represented as output space y semicolon, also do not forget to give the semicolon here. Then here you can one can see that the output y is represented as a rake data type, why? Because since the output y should store the previous value unless the next value is assigned to it. So, that is why it is defined as a rake data type. Then we write down the always block, so always block is the block which is always going to get executed continuously. So, it is like a while one in the C programming, so always and there we provide this symbol at the rate and inside the bracket we provide a statement. So, generally inside this bracket is the or operation of the inputs, so that is why it is equal to i 0 or i 1 or i 0 which are our three inputs. The meaning here is that for any valid input this i 0 or i 1 or i 0 takes this always block is going to get executed and inside there you can see the case statement. So, this case statement is similar to the C programming. So, case inside bracket you can see s 0 which is our select input. So, whenever s 0 is equal to 0 and there will be two cases since s 0 is a single bit binary number it can take either of the two values 0 or 1 and these are shown here. So, whenever s 0 is equal to 0 for that case y should be equal to i 0, so that is why y is equal to i 0 is written here and for s 0 equal to 1 y should be equal to i 1. So, that is the same thing which is written here and the case block can be should be ended with the end case statement and finally, the module is ended with the end module keyword. So, this is the module definition for 2S to 1 multiplexer. Now, let us check the test bench for 2S to 1 multiplexer. So, test bench for 2S to 1 multiplexer will also be a module it will start with the module keyword the name of the test bench is test MUX 21. The inputs are defined as a rig data type in this case because you want to provide the various input combinations of the inputs, so a rig space i 0, i 1, s 0 and the output is defined as a wire data type. The next thing is to instantiate the module which we have written for the 2S to 1 multiplexer. So, we have written MUX 21 which is the name of our module followed by the name of the object which is MO in this case you can take any name whatever name you want and inside the bracket you provide the list of input and output so i 0, i 1, s 0 and y. Then next we have to write the initial block, so initial block is written here using the initial keyword and since there are multiple statement that we want to provide here we write it in the begin and end block. So, it is a general rule in a very log that whenever there are multiple statement that you want to provide inside the initial block you write it inside the begin and end, so that is why the line here is written as initial space begin and here you provide all possible input combinations and finally this begin is end here with the end keyword whereas this initial is completed by using the end module keyword. Now, let us take a look at the input combination that are provided here, so 3 inputs are there, so i 0 is equal to 0, i 1 is equal to 0, s 0 is equal to 0 then you provide the delay that you want to provide between any 2 input combinations. So, here I have provided hash 100, the meaning here is that the delay will be 100 units and actual delay will depend on the time scale, so these 8 combinations are provided here, so before moving on to the actual simulation pause the video for 1 minute and write down the answer of the given question. I hope you have written the answer, since the output must store the previous value until next value is assigned, we declare it as the rig data type. Now, let us see the simulation results in model sim software, so I have already written the program, this is the model definition that we have discussed and this is the test bench that we have discussed in the slides. The next part is to compile the program, so go to compile, select appropriate name, so testmux21.v compile, check whether your output is correct or not and one can see here that there are no errors and warnings, so our compilation is successful, so we can go for the simulation. For simulation, go to the library and select testmux21 where you have provided the test bench, so go to simulate and then go to the add, two wave, all items in region and the next job is to run the program, so run it, so here one can analyze the waveforms as follows, three inputs are there i0, i1 and i0 and one output is there, why, so for in the first case you can see the i0 is equal to 0, i1 is equal to 0 and i0 is 0 and we know that from the function triple that whenever h0 is equal to 0 whatever is available at the i0 that will be available at the y, so that is why y is equal to 0 in this case. Take another input combination, here you can see i0 is equal to 0, i1 is equal to 1 and h0 is equal to 0, so what is going to happen in this case, the y will be equal to i0, so that is why it is still 0 in this case. In the next combination, here you can see that the i0 is equal to 0 and i1 is equal to 1 whereas, h0 is equal to 1, so since h0 is equal to 1 what should happen, y should be equal to i1, so what is the value i1 is taking, i1 is taking the value of 1, so y should be equal to 1, so the same thing you can see here that y is equal to 1 in this case, so you can also analyze the remaining input combination and if you observe this you can see that our circuit performs correctly, so the verilog model that we have written performs correctly. These are the references, thank you very much.