 Welcome to the presentation of the STM32MP1 Master Directory Memory Access Controller, or MDMA. It covers the main features of this module, which is widely used to handle data transfers. The Master Direct Memory Access, or MDMA, is optimized for data transfers between memories since it supports linked list transfers that allow performing a chained list of transfers without the need for CPU intervention. This keeps the CPU resources free for other operations. The MDMA controller provides a Master AXI interface for main memory and peripheral registers access, or system access port, and a Slave AHB interface for configuration. Each of the DMMA controller channels provides a unidirectional transfer link between a source and a destination. Each channel can perform single buffer transfer. One buffer is transferred up to 128 bytes. At the end of the buffer, the DMMA channel is disabled, and if enabled, an end-of-channel transfer interrupt is generated. Single block transfer. One block is transferred. Repeated block transfer. A number of blocks is transferred. Linked list transfer. When the transfer of the current data block, or the last block in a repeat, is completed, a new block control structure is loaded from memory, and a new block transfer is started. The MDMA also features incrementing, decrementing, or non-incrementing, or fixed addressing for source and destination. The size and address increment for both source and destination can be independently selected. MDMA is useful to collect data from all memories in the system, especially from memories on the Cortex-M4 side, and make them available to the main CPU. DMMA linked lists are used to perform a set of DMMA transfers without the need for CPU intervention. Linked lists can also be used to load configuration data into DMMA1 or DMMA2 registers and then start them. It is used to support scatter and gathering. This means that the source and destination areas do not need to occupy contiguous areas in memory. The source and destination data areas are defined by a series of linked list descriptors that control the transfer of data blocks. The MDMA supports incremental burst transfers. The size of the burst is software configurable, up to 128 bytes. For larger data sizes, the burst length is limited, as to respect the maximum data burst size of 128 bytes. For example, 16 by 64-bit or 32 by 32-bit. The size is selected using the TRGM1 to 0 trigger mode selection field. The size of the data array to be transferred for a single request will be the buffer transfer size when the TRGM or trigger mode equals 00. The size of the data array to be transferred for a single request will be the block size when the TRGM trigger mode equals 01. The size of the data array to be transferred for a single request will be a repeated block when TRGM equals 10. The size of the data array to be transferred for a single request will be a complete channel data until the linked list pointer for the channel is null when TRGM equals 11. MDMA is useful to collect data from all memories in the system, especially from memories on the Cortex-M4 side, and make them available to main CPU. DMA linked lists are used to perform a set of DMA transfers without the need for CPU intervention. Linked lists can also be used to load configuration data into DMA1 or DMA2 registers and then start them. It is used to support scatter and gathering. This means that the source and destination areas do not need to occupy contiguous areas in memory. The source and destination data areas are defined by a series of linked list descriptors that control the transfer of data blocks. Two data array size parameters have an impact on MDMA and application responsiveness. One buffer transfer size, data transfer lengths which are uninterruptible at the MDMA level from other channels requests. And two AXI burst size, it defines the maximum data transfer length which may be uninterruptible at the bus arbitration level. It is the length of the data transfer which may be transferred in burst mode, and it may block other masters from gaining access to the bus. It is important to make the correct trade-off regarding burst and buffer transfer size, considering the real-time requirements for other MDMA channels and masters. A buffer transfer is the minimum logical amount of data, up to 128 bytes, which is transferred on an MDMA request event on one channel. An MDMA buffer transfer consists of a sequence of a given number of AXI data transfers done as a single or burst data transfers. The number of data items to be transferred and their width, 8-bit, 16-bit, 32-bit or 64-bit are software programmable. The length of the burst used for data transfers is also programmable independently. After an event requiring a data array to be transferred, a request signal is sent to the MDMA controller. The MDMA controller serves the request depending on the channel priorities. The request is acknowledged by writing the mask data value to the address given in the mask address when these registers are set. A block is a contiguous array of data, up to 64 bytes, which is transferred by successive buffer transfers. Each block of data is defined by the start address and the block length. When a block transfer is completed, one of the following three actions can be executed. If the block is part of a repeated block transfer, the block length is reloaded and a new block start address is computed, based on the information in the CXBRUR register. If it is a single block or the last block in a repeated block transfer, the next block information is loaded from the memory using the linked list address information from the MDMA CXLAR. If it is the last block which needs to be transferred for the current MDMA channel, MDMA CXLAR equals zero, the channel is disabled, and no further MDMA requests will be accepted for this channel. The block repeat mode allows repetition of a block transfer, with different start addresses for source and destination. When the repeat block mode is active, the repeat counter is not equal to zero. At the end of the current block transfer, the block parameters is updated, the BNDT value reloaded, and the SARDAR values updated according to BRSUM-BRDUM configuration, and the repeat counter is decremented by one. When the repeat block counter reaches zero, this last block is treated as a single block transfer. The linked list mode allows loading of a new MDMA configuration from the address given in the CXLAR register. This address must address a memory mapped on the AXI system bus. Following this operation, the channel is ready to accept new requests, as defined in the block repeated block modes above, or continue the transfer if TRGM one to zero equals one one. The trigger source can be automatically changed when loading the CXTBR value. The TRGM and SWRM values must not be changed when TRGM one to zero equals one one. The channel configuration, channel link address LAR, must be in the AXI address space. LAR value must be aligned on a double word address boundary, such as LAR two to zero equals zero X zero. This table describes the MDMA requests and their mapping to devices. For example, an MDMA channel can be triggered by the end of transfer of the DMA one stream. In response to this trigger, the MDMA can perform data transfer from MCUSRAM one, two, three, or four to CISRAM or DDR, or reprogram the DMA one zero flow for a new transfer. To enable the MDMA to efficiently offload the CPU, MDMA channels can be triggered by devices interrupt to automate data exchanges and processing. Examples of peripheral triggers are described in this table. For each MDMA channel, an interrupt can be produced on the following events. Channel transfer completed. Block transfer completed. Block transfer repeat completed. Buffer transfer completed or transfer error. The MDMA is active in run mode. In the various stop modes, the MDMA is stopped and the contents of the MDMA registers are retained. The MDMA is powered down in standby and VBAT modes and the MDMA registers must be reinitialized after exiting these modes.